Datasheet > ATF1502AS-15QI44

ATF1502AS-15QI44

更新时间： 2024-01-18 09:14:37

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程只读存储器
页数	文件大小	规格书
18页	347K
描述
High Performance E2PROM CPLD

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技术参数
数据手册

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ATF1502AS-15QI44 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	QFP, QFP44,.5SQ,32
针数：	44	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.8
其他特性：	YES	最大时钟频率：	100 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQFP-G44
JESD-609代码：	e0	JTAG BST：	YES
长度：	10 mm	专用输入次数：
I/O 线路数量：	32	宏单元数：	32
端子数量：	44	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	0 DEDICATED INPUTS, 32 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP44,.5SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	240	电源：	3.3,5 V
可编程逻辑类型：	EE PLD	传播延迟：	15 ns
认证状态：	Not Qualified	座面最大高度：	2.45 mm
子类别：	Programmable Logic Devices	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	10 mm	Base Number Matches：	1

ATF1502AS-15QI44 数据手册

macrocell. (This feature is automatically implemented by

the fitter software). In addition to D, T, JK and SR opera-

tion, the flip flop can also be configured as a flow-through

latch. In this mode, data passes through when the clock is

high and is latched when the clock is low.

This circuitry prevents unused input and I/O lines from

floating to intermediate voltage levels, which cause unnec-

essary power consumption and system noise. The keeper

circuits eliminate the need for external pull-up resistors and

eliminate their DC power consumption.

The clock itself can either be one of the Global CLK Signal

GCK[0 : 2] or an individual product term. The flip flop

changes state on the clock’s rising edge. When the GCK

signal is used as the clock, one of the macrocell product

terms can be selected as a clock enable. When the clock

enable function is active and the enable signal (product

term) is low, all clock edges are ignored. The flip flop’s

asynchronous reset signal (AR) can be either the Global

Clear (GCLEAR), a product term, or always off. AR can

also be a logic OR of GCLEAR with a product term. The

asynchronous preset (AP) can be a product term or always

off.

Input Diagram

Output Select and Enable

The ATF1502AS macrocell output can be selected as reg-

istered or combinatorial. The buried feedback signal can be

either combinatorial or registered signal regardless of

whether the output is combinatorial or registered.

I/O Diagram

The output enable multiplexer (MOE) controls the output

enable signals. Any buffer can be permanently enabled for

simple output operation. Buffers can also be permanently

disabled to allow use of the pin as an input. In this configu-

ration all the macrocell resources are still available, includ-

ing the buried feedback, expander and CASCADE logic.

The output enable for each macrocell can be selected as

either of the two dedicated OE input pins as an I/O pin con-

figured as an input, or as an individual product term.

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well

as the buried feedback signal from all 32 macrocells. The

Switch Matrix in each Logic Block receives as its inputs all

signals from the global bus. Under software control, up to

40 of these signals can be selected as inputs to the Logic

Block.

Speed/Power Management

The ATF1502AS has several built-in speed and power

management features. The ATF1502AS contains circuitry

that automatically puts the device into a low power stand-

by mode when no logic transitions are occurring. This not

only reduces power consumption during inactive periods,

but also provides a proportional power savings for most

applications running at system speeds below 50 MHz. This

feature may be selected as a design option.

Foldback Bus

Each macrocell also generates a foldback product term.

This signal goes to the regional bus and is available to 4

macrocells. The foldback is an inverse polarity of one of the

macrocell’s product terms. The 4 foldback terms in each

region allows generation of high fan-in sum terms (up to 9

product terms) with a small additional delay.

To further reduce power, each ATF1502AS macrocell has

a Reduced Power bit feature. This feature allows individual

macrocells to be configured for maximum power savings.

This feature may be selected as a design option.

Programmable Pin-Keeper Option for

Inputs and I/Os

The ATF1502AS offers the option of programming all input

and I/O pins so that pin keeper circuits can be utilized.

When any pin is driven high or low and then subsequently

left floating, it will stay at that previous high or low level.

The ATF1502ASs also has an optional power down mode.

In this mode, current drops to below 10 mA. When the

power down option is selected, either PD1 or PD2 pins (or

both) can be used to power down the part. The power down

ATF1502AS

1 2 345 6 7...18

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与ATF1502AS-15QI44相关器件

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ATF1502AS-25AU44	ATMEL	EE PLD, 25ns, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, T	获取价格
ATF1502AS-25JU44	ATMEL	EE PLD, 25ns, PQCC44, GREEN, PLASTIC, MS-018AC, LCC-44	获取价格
ATF1502AS-7AC44	ATMEL	High Performance E2PROM CPLD	获取价格
ATF1502AS-7AL44	ATMEL	EE PLD, 7.5ns, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-44	获取价格
ATF1502AS-7AX44	ATMEL	Highperformance EEPROM CPLD	获取价格
ATF1502AS-7AX44-T	MICROCHIP	7NS TQFP COM TEMP GREEN	获取价格

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