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ATF1502AS-15QI44 PDF预览

ATF1502AS-15QI44

更新时间: 2024-01-14 21:33:37
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器
页数 文件大小 规格书
18页 347K
描述
High Performance E2PROM CPLD

ATF1502AS-15QI44 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFP, QFP44,.5SQ,32
针数:44Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.8
其他特性:YES最大时钟频率:100 MHz
系统内可编程:YESJESD-30 代码:S-PQFP-G44
JESD-609代码:e0JTAG BST:YES
长度:10 mm专用输入次数:
I/O 线路数量:32宏单元数:32
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C组织:0 DEDICATED INPUTS, 32 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP44,.5SQ,32
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):240电源:3.3,5 V
可编程逻辑类型:EE PLD传播延迟:15 ns
认证状态:Not Qualified座面最大高度:2.45 mm
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

ATF1502AS-15QI44 数据手册

 浏览型号ATF1502AS-15QI44的Datasheet PDF文件第1页浏览型号ATF1502AS-15QI44的Datasheet PDF文件第2页浏览型号ATF1502AS-15QI44的Datasheet PDF文件第4页浏览型号ATF1502AS-15QI44的Datasheet PDF文件第5页浏览型号ATF1502AS-15QI44的Datasheet PDF文件第6页浏览型号ATF1502AS-15QI44的Datasheet PDF文件第7页 
ATF1502AS  
Each macrocell also generates a foldback logic term, which  
goes to a regional bus. Cascade logic between macrocells  
in the ATF1502AS allows fast, efficient generation of com-  
plex logic functions. The ATF1502AS contains four such  
logic chains, each capable of creating sum term logic with a  
fan in of up to 40 product terms.  
when programmed, protects the contents of the  
ATF1502AS. Two bytes (16-bits) of User Signature are  
accessible to the user for purposes such as storing project  
name, part number, revision or date. The User Signature is  
accessible regardless of the state of the Security Fuse.  
The ATF1502AS device is an In-System Programmable  
(ISP) device. It uses the industry standard 4-pin JTAG  
interface (IEEE Std. 1149.1), and is fully compliant with  
JTAG’s Boundary Scan Description Language (BSDL). ISP  
allows the device to be programmed without removing it  
from the printed circuit board. In addition to simplifying the  
manufacturing flow, ISP also allows design modifications to  
be made in the field via software.  
The ATF1502AS macrocell shown in Figure 1, is flexible  
enough to support highly complex logic functions operating  
at high speed. The macrocell consists of five sections:  
product terms and product term select multiplexer;  
OR/XOR/CASCADE logic; a flip-flop; output select and  
enable; and logic array inputs.  
Unused product terms are automatically disabled by the  
compiler to decrease power consumption. A Security Fuse,  
Figure 1. ATF1502AS Macrocell  
Product Terms and Select MUX  
many as 40 product terms with a very small additional  
delay.  
Each ATF1502AS macrocell has five product terms. Each  
product term receives as its inputs all signals from both the  
global bus and regional bus.  
The macrocell’s XOR gate allows efficient implementation  
of compare and arithmetic functions. One input to the XOR  
comes from the OR sum term. The other XOR input can be  
a product term or a fixed high or low level. For combinato-  
rial outputs, the fixed level input allows polarity selection.  
For registered functions, the fixed levels allow DeMorgan  
minimization of product terms. The XOR gate is also used  
to emulate T- and JK-type flip-flops.  
The product term select multiplexer (PTMUX) allocates the  
five product terms as needed to the macrocell logic gates  
and control signals. The PTMUX programming is deter-  
mined by the design compiler, which selects the optimum  
macrocell configuration.  
OR/XOR/CASCADE Logic  
Flip Flop  
The ATF1502AS’s logic structure is designed to efficiently  
support all types of logic. Within a single macrocell, all the  
product terms can be routed to the OR gate, creating a 5-  
input AND/OR sum term. With the addition of the CASIN  
from neighboring macrocells, this can be expanded to as  
The ATF1502AS’s flip flop has very flexible data and con-  
trol functions. The data input can come from either the XOR  
gate, from a separate product term or directly from the I/O  
pin. Selecting the separate product term allows creation of  
a buried registered feedback within a combinatorial output  
3

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