44-Lead TQFP/PQFP
Top View
44-Lead PLCC
Top View
TDI/I/O
I/O
7
8
9
39 I/O
I/O/TDI
I/O
1
2
3
4
5
6
7
8
9
33 I/O
38 I/O/TDO
37 I/O
32 I/O/TDO
31 I/O
I/O
I/O
GND 10
PD1/I/O 11
I/O 12
36 I/O
GND
PD1/I/O
I/O
30 I/O
35 VCC
34 I/O
29 VCC
28 I/O
TMS/I/O
I/O
27 I/O
I/O/TMS 13
I/O 14
33 I/O
26 I/O/TCK
25 I/O
32 I/O/TCK
31 I/O
VCC
VCC 15
I/O 16
I/O 10
I/O 11
24 GND
23 I/O
30 GND
29 I/O
I/O 17
Description
The ATF1502AS is a high performance, high density Com-
plex Programmable Logic Device (CPLD) which utilizes
Atmel’s proven electrically erasable technology. With 32
logic macrocells and up to 36 inputs, it easily integrates
logic from several TTL, SSI,MSI, LSI and classic PLDs.
The ATF1502AS’s enhanced routing switch matrices
increase usable gate count, and the odds of successful pin-
locked design modifications.
The ATF1502AS has up to 32 bi-directional I/O pins and 4
dedicated input pins, depending on the type of device pack-
age selected. Each dedicated pin can also serve as a glo-
bal control signal; register clock, register reset or output
enable. Each of these control signals can be selected for
use individually within each macrocell.
Block Diagram
B
32
Each of the 32 macrocells generates a buried feedback,
which goes to the global bus. Each input and I/O pin also
feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus.
ATF1502AS
2