Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF1502AS-10JU44

ATF1502AS-10JU44

更新时间： 2024-02-25 12:52:19

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件输入元件异步传输模式 PC ATM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
26页	517K
描述
Highperformance EEPROM CPLD

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技术参数
数据手册

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ATF1502AS-10JU44 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	QCCJ, LDCC44,.7SQ
Reach Compliance Code：	compliant	Factory Lead Time：	18 weeks
风险等级：	1.47	Samacsys Confidence：	4
Samacsys Status：	Released	Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=468582
PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=468582	Samacsys PartID：	468582
Samacsys Image：	https://componentsearchengine.com/Images/9/ATF1502AS-10JU44.jpg	Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/1/ATF1502AS-10JU44.jpg
Samacsys Pin Count：	44	Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Plastic Leaded Chip Carrier	Samacsys Footprint Name：	44J - PLCC
Samacsys Released Date：	2019-10-16 11:57:55	Is Samacsys：	N
其他特性：	YES	最大时钟频率：	125 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e3	JTAG BST：	YES
长度：	16.586 mm	湿度敏感等级：	3
专用输入次数：		I/O 线路数量：	32
宏单元数：	32	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 32 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	245
电源：	3.3,5 V	可编程逻辑类型：	EE PLD
传播延迟：	10 ns	认证状态：	Not Qualified
座面最大高度：	4.572 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	16.586 mm
Base Number Matches：	1

ATF1502AS-10JU44 数据手册

ATF1502AS(L)

The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual prod-

uct term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used

as the clock, one of the macrocell product terms can be selected as a clock enable. When the

clock enable function is active and the enable signal (product term) is low, all clock edges are

ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear

(GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a prod-

uct term. The asynchronous preset (AP) can be a product term or always off.

Extra Feedback

The ATF1502AS(L) macrocell output can be selected as registered or combinatorial. The

extra buried feedback signal can be either combinatorial or a registered signal regardless of

whether the output is combinatorial or registered. (This enhancement function is automatically

implemented by the fitter software.) Feedback of a buried combinatorial output allows the cre-

ation of a second latch within a macrocell.

I/O Control

The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-

vidually configured as an input, output or for bi-directional operation. The output enable for

each macrocell can be selected from the true or compliment of the two output enable pins, a

subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done

by the fitter software when the I/O is configured as an input, all macrocell resources are still

available, including the buried feedback, expander and cascade logic.

Global Bus/Switch

Matrix

The global bus contains all input and I/O pin signals as well as the buried feedback signal from

all 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from

the global bus. Under software control, up to 40 of these signals can be selected as inputs to

the logic block.

Foldback Bus

Each macrocell also generates a foldback product term. This signal goes to the regional bus

and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s

product terms. The four foldback terms in each region allow generation of high fan-in sum

terms (up to nine product terms) with little additional delay.

Programmable

Pin-keeper

Option for

The ATF1502AS offers the option of programming all input and I/O pins so that pin-keeper cir-

cuits can be utilized. When any pin is driven high or low and then subsequently left floating, it

will stay at that previous high or low level. This circuitry prevents unused input and I/O lines

from floating to intermediate voltage levels, which causes unnecessary power consumption

and system noise. The keeper circuits eliminate the need for external pull-up resistors and

eliminate their DC power consumption.

Inputs and I/Os

0995K–PLD–6/05

1 2 3 456 7 8...26

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ATF1502AS-15AJ44	ATMEL	EE PLD, 15ns, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-44	获取价格
ATF1502AS-15AL44	ATMEL	EE PLD, 15ns, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-44	获取价格

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