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ATF1500AL-25AI PDF预览

ATF1500AL-25AI

更新时间: 2024-02-18 23:29:47
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件
页数 文件大小 规格书
16页 683K
描述
High Performance E2 PLD

ATF1500AL-25AI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LPCC包装说明:QCCJ, LDCC44,.7SQ
针数:44Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.82
Is Samacsys:N其他特性:NO
最大时钟频率:43 MHz系统内可编程:NO
JESD-30 代码:S-PQCC-J44JESD-609代码:e0
JTAG BST:NO长度:16.5862 mm
湿度敏感等级:2专用输入次数:
I/O 线路数量:32宏单元数:32
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C组织:0 DEDICATED INPUTS, 32 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC44,.7SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225电源:5 V
可编程逻辑类型:FLASH PLD传播延迟:25 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:16.5862 mmBase Number Matches:1

ATF1500AL-25AI 数据手册

 浏览型号ATF1500AL-25AI的Datasheet PDF文件第1页浏览型号ATF1500AL-25AI的Datasheet PDF文件第2页浏览型号ATF1500AL-25AI的Datasheet PDF文件第3页浏览型号ATF1500AL-25AI的Datasheet PDF文件第5页浏览型号ATF1500AL-25AI的Datasheet PDF文件第6页浏览型号ATF1500AL-25AI的Datasheet PDF文件第7页 
ATF1500A/AL Macrocell  
ATF1500A Macrocell  
The ATF1500A macrocell is flexible enough to support  
highly complex logic functions operating at high speed. The  
macrocell consists of five sections: product terms and prod-  
uct term select multiplexer; OR/XOR/CASCADE logic; a flip  
flop; output select and enable; and logic array inputs.  
routed to the OR gate, creating a five input AND/OR sum  
term. With the addition of the CASIN from neighboring  
macrocells, this can be expanded to as many as 40 product  
terms with a very small additional delay.  
The macrocell's XOR gate allows efficient implementation  
of compare and arithmetic functions. One input to the XOR  
comes from the OR sum term. The other XOR input can be  
a product term or a fixed high or low level. For combinato-  
rial outputs, the fixed level input allows output polarity  
selection. For registered functions, the fixed levels allow De  
Morgan minimization of the product terms. The XOR gate is  
also used to emulate JK type flip flops.  
Product Terms and Select Mux  
Each ATF1500A macrocell has five product terms. Each  
product term receives as its inputs all signals from both the  
global bus and regional bus.  
The product term select multiplexer (PTMUX) allocates the  
five product terms as needed to the macrocell logic gates  
and control signals. The PTMUX programming is deter-  
mined by the design compiler, which selects the optimum  
macrocell configuration.  
Flip Flop  
The ATF1500A's flip flop has very flexible data and control  
functions. The data input can come from either the XOR  
gate or from a separate product term. Selecting the sepa-  
rate product term allows creation of a buried registered  
feedback within a combinatorial output macrocell.  
OR/XOR/CASCADE Logic  
The ATF1500A macrocell's OR/XOR/CASCADE logic  
structure is designed to efficiently support all types of logic.  
Within a single macrocell, all the product terms can be  
(continued)  
ATF1500A/AL  
4

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