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ATF1500ABV-15JC PDF预览

ATF1500ABV-15JC

更新时间: 2024-01-29 23:08:09
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
12页 296K
描述
High- Performance EE PLD

ATF1500ABV-15JC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:LCC包装说明:QCCJ,
针数:44Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.61
最大时钟频率:52.6 MHzJESD-30 代码:S-PQCC-J44
JESD-609代码:e3长度:16.5862 mm
湿度敏感等级:2专用输入次数:
I/O 线路数量:32端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
组织:0 DEDICATED INPUTS, 32 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245可编程逻辑类型:FLASH PLD
传播延迟:15 ns认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压:5.5 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:16.5862 mm

ATF1500ABV-15JC 数据手册

 浏览型号ATF1500ABV-15JC的Datasheet PDF文件第1页浏览型号ATF1500ABV-15JC的Datasheet PDF文件第2页浏览型号ATF1500ABV-15JC的Datasheet PDF文件第3页浏览型号ATF1500ABV-15JC的Datasheet PDF文件第5页浏览型号ATF1500ABV-15JC的Datasheet PDF文件第6页浏览型号ATF1500ABV-15JC的Datasheet PDF文件第7页 
ATF1500ABV Macrocell  
ATF1500ABV Macrocell  
The ATF1500ABV macrocell is flexible enough to support  
highly complex logic functions operating at high speed. The  
macrocell consists of five sections: product terms and prod-  
uct term select multiplexer; OR/XOR/CASCADE logic; a flip  
flop; output select and enable; and logic array inputs.  
term. With the addition of the CASIN from neighboring  
macrocells, this can be expanded to as many as 40 product  
terms with a very small additional delay.  
The macrocell's XOR gate allows efficient implementation  
of compare and arithmetic functions. One input to the XOR  
comes from the OR sum term. The other XOR input can be  
a product term or a fixed high or low level. For combinato-  
rial outputs, the fixed level input allows output polarity  
selection. For registered functions, the fixed levels allow De  
Morgan minimization of the product terms. The XOR gate is  
also used to emulate JK type flip flops.  
Product Terms and Select Mux  
Each ATF1500ABV macrocell has five product terms. Each  
product term receives as its inputs all signals from both the  
global bus and regional bus.  
The product term select multiplexer (PTMUX) allocates the  
five product terms as needed to the macrocell logic gates  
and control signals. The PTMUX programming is deter-  
mined by the design compiler, which selects the optimum  
macrocell configuration.  
Flip Flop  
The ATF1500ABV’s flip flop has very flexible data and con-  
trol functions. The data input can come from either the XOR  
gate or from a separate product term. Selecting the sepa-  
rate product term allows creation of a buried registered  
feedback within a combinatorial output macrocell.  
OR/XOR/CASCADE Logic  
The ATF1500ABV macrocell's OR/XOR/CASCADE logic  
structure is designed to efficiently support all types of logic.  
Within a single macrocell, all the product terms can be  
routed to the OR gate, creating a five input AND/OR sum  
In addition to D, T, JK and SR operation, the flip flop can  
also be configured as a flow-through latch. In this mode,  
ATF1500ABV/L  
4

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