Datasheet > ATF1500ABV-15AJ

ATF1500ABV-15AJ

更新时间： 2024-02-28 17:10:44

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟输入元件可编程逻辑
页数	文件大小	规格书
15页	317K
描述
Flash PLD, 15ns, CMOS, PQFP44, 1 MM HEIGHT, PLASTIC, TQFP-44

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ATF1500ABV-15AJ 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	TQFP,
针数：	44	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.76
最大时钟频率：	52.6 MHz	JESD-30 代码：	S-PQFP-G44
JESD-609代码：	e3	长度：	10 mm
湿度敏感等级：	3	专用输入次数：
I/O 线路数量：	32	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 32 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE
峰值回流温度（摄氏度）：	260	可编程逻辑类型：	FLASH PLD
传播延迟：	15 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压：	5.5 V
最小供电电压：	2.7 V	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	10 mm	Base Number Matches：	1

ATF1500ABV-15AJ 数据手册

ATF1500ABV

The ATF1500ABV’s 100% connected global input and feedback architecture simplifies logic

placement and eliminates pinout changes due to design changes. Any Macrocell may be con-

nected to any I/O pin.

The ATF1500ABV has 32 bi-directional I/O pins and four dedicated input pins. Each dedicated

input pin can also serve as a global control signal: register clock, register reset or output

enable. Each of these control signals can be selected for use individually within each

macrocell.

Each of the 32 logic macrocells generates a buried feedback, which goes to the global bus.

Each input and I/O pin also feeds into the global bus. Because of this global busing, each of

these signals is always available to all 32 macrocells in the device.

Each macrocell also generates a foldback logic term, which goes to a regional bus. All signals

within a regional bus are connected to all 16 macrocells within the region.

Cascade logic between macrocells in the ATF1500ABV allows fast, efficient generation of

complex logic functions. The ATF1500ABV contains four such logic chains, each capable of

creating sum term logic with a fan-in of up to 40 product terms.

Bus-friendly

Pin-keeper

Input and I/Os

All input and I/O pins on the ATF1500ABV have programmable “data-keeper” circuits. If acti-

vated, when any pin is driven high or low and then subsequently left floating, it will stay at that

previous high or low level.

This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels

that cause unnecessary power consumption and system noise. The keeper circuits eliminate

the need for external pull-up resistors and eliminate their DC power consumption.

Pin-keeper circuits can be disabled. Programming is controlled in the logic design file. Once

the pin-keeper circuits are disabled, normal termination procedures are required for unused

inputs and I/Os.

Speed/Power

Management

The ATF1500ABV has several built-in speed and power management features. The

ATF1500ABV contains circuitry that automatically puts the device into a low-power standby

mode when no logic transitions are occurring. This not only reduces power consumption dur-

ing inactive periods, but also provides proportional power savings for most applications

running at system speeds below 10 MHz.

All ATF1500ABVs also have an optional pin-controlled power-down mode. In this mode, cur-

rent drops to typically 2 mA. When the power-down option is selected, the PD pin is used to

power-down the part. The power-down option is selected in the design source file. When

enabled, the device goes into power-down when the PD pin is high. In the power-down mode,

all internal logic signals are latched and held, as are any enabled outputs. All pin transitions

are ignored until the PD is brought low. When the power-down feature is enabled, the PD can-

not be used as a logic input or output. However, the PD pin’s macrocell may still be used to

generate buried foldback and cascade logic signals.

Each output also has individual slew rate control. This may be used to reduce system noise by

slowing down outputs that do not need to operate at maximum speed. Outputs default to slow

switching, and may be specified as fast switching in the design file.

0723I–08/01

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ATF1500ABV-15JC	ATMEL	High- Performance EE PLD	获取价格
ATF1500ABV-15JI	ATMEL	High- Performance EE PLD	获取价格
ATF1500ABV-15JJ	ATMEL	Flash PLD, 15ns, CMOS, PQCC44, PLASTIC, LCC-44	获取价格
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