Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF1500A-15JI

ATF1500A-15JI

更新时间： 2024-02-10 07:43:51

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件
页数	文件大小	规格书
16页	683K
描述
High Performance E2 PLD

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技术参数
数据手册

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ATF1500A-15JI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	QFP, TQFP44,.47SQ,32	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.57
其他特性：	NO	系统内可编程：	NO
JESD-30 代码：	S-PQFP-G44	JESD-609代码：	e3
JTAG BST：	NO	湿度敏感等级：	2
宏单元数：	32	端子数量：	44
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	TQFP44,.47SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	245
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	15 ns	认证状态：	Not Qualified
子类别：	Programmable Logic Devices	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	Base Number Matches：	1

ATF1500A-15JI 数据手册

ATF1500A/AL

The ATF1500A has 32 bi-directional I/O pins and 4 dedi-

cated input pins. Each dedicated input pin can also serve

as a global control signal: register clock, register reset or

output enable. Each of these control signals can be

selected for use individually within each macrocell.

Speed/Power Management

The ATF1500A has several built-in speed and power man-

agement features. The ATF1500A contains circuitry that

automatically puts the device into a low power stand-by

mode when no logic transitions are occurring. This not only

reduces power consumption during inactive periods, but

also provides a proportional power savings for most appli-

cations running at system speeds below 10 MHz.

Each of the 32 logic macrocells generates a buried feed-

back, which goes to the global bus. Each input and I/O pin

also feeds into the global bus. Because of this global bus-

sing, each of these signals is always available to all 32

macrocells in the device.

All ATF1500As also have an optional pin-controlled power

down mode. In this mode, current drops to below 10 µA.

When the power down option is selected, the PD pin is

used to power down the part. The power down option is

selected in the design source file. When enabled, the

device goes into power down when the PD pin is high. In

the power down mode, all internal logic signals are latched

and held, as are any enabled outputs. All pin transitions are

ignored until the PD is brought low. When the power down

feature is enabled, the PD cannot be used as a logic input

or output. However, the PD pin's macrocell may still be

used to generate buried foldback and cascade logic sig-

nals.

Each macrocell also generates a foldback logic term, which

goes to a regional bus. All signals within a regional bus are

connected to all 16 macrocells within the region.

Cascade logic between macrocells in the ATF1500A allows

fast, efficient generation of complex logic functions. The

ATF1500A contains 4 such logic chains, each capable of

creating sum term logic with a fan in of up to 40 product

terms.

Bus Friendly Pin-Keeper Input and I/O’s

All Input and I/O pins on the ATF1500A have programma-

ble “data keeper” circuits. If activated, when any pin is

driven high or low and then subsequently left floating, it will

stay at that previous high or low level.

Each output also has individual slew rate control. This may

be used to reduce system noise by slowing down outputs

that do not need to operate at maximum speed. Outputs

default to slow switching, and may be specified as fast

switching in the design file.

This circuitry prevents unused Input and I/O lines from

floating to intermediate voltage levels, which cause unnec-

essary power consumption and system noise. The keeper

circuits eliminate the need for external pull-up resistors and

eliminate their DC power consumption.

Design Software Support

ATF1500A designs are supported by several 3rd party

tools. Automated fitters allow logic synthesis using a variety

of high level description languages and formats.

Pin-keeper circuits can be disabled. Programming is con-

trolled in the logic design file. Once the pin-keeper circuits

are disabled, normal termination procedures are required

for unused inputs and I/Os.

Input Diagram

I/O Diagram

V_CC

DATA

I/O

INPUT

100K

V_CC

ESD

PROTECTION

CIRCUIT

PROGRAMMABLE

OPTION

100K

PROGRAMMABLE

OPTION

1 234 5 6 7...16

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与ATF1500A-15JI相关器件

型号	品牌	描述	获取价格	数据表
ATF1500A-15JJ	ATMEL	Flash PLD, 15ns, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44	获取价格
ATF1500A-15JL	ATMEL	Flash PLD, 15ns, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44	获取价格
ATF1500A-15JU	ATMEL	EE PLD	获取价格
ATF1500A-20AC	ATMEL	Flash PLD, 20ns, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-	获取价格
ATF1500A-20AI	ATMEL	Flash PLD, 20ns, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-	获取价格
ATF1500A-20JC	ATMEL	Flash PLD, 20ns, PQCC44, PLASTIC, MS-018AC, LCC-44	获取价格

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