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ATA6837_09 PDF预览

ATA6837_09

更新时间: 2022-12-27 23:39:48
品牌 Logo 应用领域
爱特美尔 - ATMEL 驱动器
页数 文件大小 规格书
18页 376K
描述
High Temperature Hex Half-bridge Driver with Serial Input Control

ATA6837_09 数据手册

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ATA6837  
3. Functional Description  
3.1  
Serial Interface  
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized  
to CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-  
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS  
is high, pin DO is in a tri-state condition. This output is enabled on the falling edge of CS. Output  
data will change their state with the rising edge of CLK and stay stable until the next rising edge  
of CLK appears. LSB (bit 0, TP) is transferred first.  
Figure 3-1. Data Transfer Input Data Protocol  
CS  
DI  
CLK  
DO  
SRR  
0
LS1  
HS1  
LS2  
HS2  
LS3  
HS3  
LS4  
HS4  
LS5  
HS5  
10  
LS6  
11  
HS6  
12  
SCT  
14  
SI  
OLD  
13  
1
2
3
4
5
6
7
8
9
15  
TP  
SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD  
INH  
PSF  
Table 3-1.  
Bit  
Input Data Protocol  
Input Register  
Function  
Status register reset (high = reset; the bits PSF, SCD and  
overtemperature shutdown in the output data register are set to low)  
0
SRR  
1
2
LS1  
HS1  
LS2  
HS2  
LS3  
HS3  
LS4  
HS4  
LS5  
HS5  
LS6  
HS6  
OLD  
Controls output LS1 (high = switch output LS1 on)  
Controls output HS1 (high = switch output HS1 on)  
3
See LS1  
4
See HS1  
5
See LS1  
6
See HS1  
7
See LS1  
8
See HS1  
9
See LS1  
10  
11  
12  
13  
See HS1  
See LS1  
See HS1  
Open load detection (low = on)  
Programmable time delay for short circuit  
(shutdown delay high/low = 12 ms/1.5 ms)  
14  
SCT  
Software inhibit; low = standby, high = normal operation  
(data transfer is not affected by standby function because the digital  
part is still powered)  
15  
SI  
5
4953E–AUTO–09/09  

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