ATA6837
2. Pin Configuration
Figure 2-1. Pinning QFN 24, 5 × 5, 0.65 mm pitch
24 23 22 21 20 19
OUT4 SENSE
OUT4
1
2
3
4
5
6
18 CLK
17 CS
VS
16 GND SENSE
15 NC
VS
OUT3
14 VCC
OUT3 SENSE
13 DO
7
8 9 10 11 12
Note:
YWW
ATAxyz
ZZZZZ
AL
Date code (Y = Year above 2000, WW = week number)
Product name
Wafer lot number
Assembly sub-lot number
Table 2-1.
Pin Description QFN24
Symbol Function
OUT4 SENSE Only for testability in final test
Pin
1
Half-bridge output 4; formed by internally connected power MOS high-side switch 4 and low-side switch 4
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
2
OUT4
3
4
VS
VS
Power supply output stages HS4, HS5 and HS6
Power supply output stages HS1, HS2 and HS3
Output 3; see pin 1
5
OUT3
6
OUT3 SENSE Only for testability in final test
7
NC
Internal bond to GND
Output 2; see pin 1
8
OUT2
9
OUT2 SENSE Only for testability in final test
OUT1 SENSE Only for testability in final test
10
11
12
OUT1
INH
Output 1; see pin 1
Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operation
Serial data output; 5V CMOS logic level tri-state output for output (status) register data; sends 16-bit status
information to the microcontroller (LSB is transferred first). Output will remain tri-stated unless device is
selected by CS = low, therefore, several ICs can operate on one data output line only
13
DO
14
15
16
VCC
NC
Logic supply voltage (5V)
Internal bond to GND
GND SENSE Ground; reference potential; internal connection to the lead frame; cooling tab
3
4953E–AUTO–09/09