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ATA6630-GLQW PDF预览

ATA6630-GLQW

更新时间： 2024-01-22 00:29:45
品牌 Logo 应用领域
爱特美尔 - ATMEL 以太网：16GBASE-T电信电信集成电路
页数 文件大小 规格书
36页 1218K
描述
Ethernet Transceiver, 5 X 5 MM, LEAD FREE, VQFN-20

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ATA6630-GLQW 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended包装说明：HVQCCN,
Reach Compliance Code：compliant风险等级：5.68
JESD-30 代码：S-XQCC-N20JESD-609代码：e3
长度：5 mm功能数量：1
端子数量：20封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE座面最大高度：0.9 mm
表面贴装：YES电信集成电路类型：ETHERNET TRANSCEIVER
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.65 mm端子位置：QUAD
宽度：5 mmBase Number Matches：1

ATA6630-GLQW 数据手册

 浏览型号ATA6630-GLQW的Datasheet PDF文件第3页浏览型号ATA6630-GLQW的Datasheet PDF文件第4页浏览型号ATA6630-GLQW的Datasheet PDF文件第5页浏览型号ATA6630-GLQW的Datasheet PDF文件第7页浏览型号ATA6630-GLQW的Datasheet PDF文件第8页浏览型号ATA6630-GLQW的Datasheet PDF文件第9页 
3.17 WD_OSC Output Pin  
The WD_OSC Output pin provides a typical voltage of 1.2V, which supplies an external resistor with values between 34kΩ  
and 120kΩ to adjust the watchdog oscillator time.  
If the watchdog is disabled, this voltage is switched off and you can either tie to GND or leave this pin open.  
3.18 NTRIG Input Pin  
The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge  
followed by a low phase longer than ttrigmin triggers the watchdog.  
3.19 Wake-up Events from Sleep or Silent Mode  
●
●
●
●
LIN-bus  
WAKE pin  
EN pin  
KL_15  
3.20 DIV_ON Input Pin  
The DIV_ON pin is a low voltage input. It is used to switch on or off the internal voltage divider PV output directly with no time  
limitation (see Table 3-1 on page 6). It is switched on if DIV_ON is high or it is switched off if DIV_ON is low. In Sleep Mode  
the DIV_ON functionality is disabled and PV is off. An internal pull-down resistor is implemented.  
3.21 VBATT Input Pin  
The VBATT is a high voltage input pin to supply the internal voltage divider. In an application with battery voltage monitoring,  
this pin is connected to VBattery via a 47Ω resistor in series and a 10nF capacitor to GND (see Figure 9-2 on page 31). The  
divider ratio is 1:6.  
3.22 PV Output Pin  
For applications with battery monitoring, this pin is directly connected to the ADC of a microcontroller. For buffering the ADC  
input an external capacitor might be needed. This pin guarantees a voltage and temperature stable output of a VBattery ratio.  
The PV output pin is controlled by the DIV_ON input pin.  
Table 3-1. Table of Voltage Divider  
Mode of Operation  
Input DiV_ON  
Voltage Divider Output PV  
0
1
0
1
Off  
On  
Off  
Off  
Fail-safe/Normal/  
High-speed/Silent  
Sleep  
3.23 SP_MODE Input Pin  
The SP_MODE pin is a low-voltage input. High-speed Mode of the transceiver can be activated via a high level during  
Normal Mode. Return to LIN 2.x Transceiver Mode with slope control is possible if you switch the SP_MODE pin to low.  
6
ATA6628/ATA6630 [DATASHEET]  
9117I–AUTO–10/14  
1...3456789...36

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