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ATA6630-GLQW PDF预览

ATA6630-GLQW

更新时间： 2024-01-07 14:44:48
品牌 Logo 应用领域
爱特美尔 - ATMEL 以太网：16GBASE-T电信电信集成电路
页数 文件大小 规格书
36页 1218K
描述
Ethernet Transceiver, 5 X 5 MM, LEAD FREE, VQFN-20

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ATA6630-GLQW 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended包装说明：HVQCCN,
Reach Compliance Code：compliant风险等级：5.68
JESD-30 代码：S-XQCC-N20JESD-609代码：e3
长度：5 mm功能数量：1
端子数量：20封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE座面最大高度：0.9 mm
表面贴装：YES电信集成电路类型：ETHERNET TRANSCEIVER
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.65 mm端子位置：QUAD
宽度：5 mmBase Number Matches：1

ATA6630-GLQW 数据手册

 浏览型号ATA6630-GLQW的Datasheet PDF文件第1页浏览型号ATA6630-GLQW的Datasheet PDF文件第2页浏览型号ATA6630-GLQW的Datasheet PDF文件第3页浏览型号ATA6630-GLQW的Datasheet PDF文件第5页浏览型号ATA6630-GLQW的Datasheet PDF文件第6页浏览型号ATA6630-GLQW的Datasheet PDF文件第7页 
3.  
Functional Description  
3.1  
Physical Layer Compatibility  
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical  
layer according to revision 2.x can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0,  
LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions.  
3.2  
Supply Pin (VS)  
The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if VS  
falls below VSth in order to avoid false bus messages. After switching on VS, the IC starts in Fail-safe Mode, and the voltage  
regulator is switched on (i.e., 3.3V/5V/85mA output capability).  
The supply current is typically 10µA in Sleep Mode and 35µA in Silent Mode.  
3.3  
3.4  
Ground Pin (GND)  
The Atmel® ATA6628/ATA6630 does not affect the LIN Bus in the event of GND disconnection. It is able to handle a ground  
shift up to 11.5% of VS. The mandatory system ground is pin 5.  
Voltage Regulator Output Pin (VCC)  
The internal 3.3V/5V voltage regulator is capable of driving loads up to 85mA. It is able to supply the microcontroller and  
other ICs on the PCB and is protected against overloads by means of current limitation and overtemperature shut-down.  
Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined  
threshold Vthun. To boost up the maximum load current, an external NPN transistor may be used, with its base connected to  
the VCC pin and its emitter connected to PVCC.  
3.5  
3.6  
Voltage Regulator Sense Pin (PVCC)  
The PVCC is the sense input pin of the 3.3V/5V voltage regulator. For normal applications (i.e., when only using the internal  
output transistor), this pin must be connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must  
be connected to the output of this transistor, i.e., its emitter terminal.  
Bus Pin (LIN)  
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN  
2.x specification are implemented. The allowed voltage range is between –27V and +40V. Reverse currents from the LIN  
bus to VS are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible  
with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to  
recessive bus state are slope controlled.  
3.7  
3.8  
Input/Output Pin (TXD)  
In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled  
to ground in order to have a low LIN-bus. If TXD is high or not connected (internal pull-up resistor), the LIN output transistor  
is turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output and is signalling the fail-safe  
source. It is current-limited to < 8mA.  
TXD Dominant Time-out Function  
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in  
dominant state. If TXD is forced to low for longer than tDOM, the LIN-bus driver is switched to recessive state. Nevertheless,  
when switching to Sleep Mode, the actual level at the TXD pin is relevant.  
To reactivate the LIN bus driver after a TXD time-out has occurred, switch TXD to high (> 10µs).  
4
ATA6628/ATA6630 [DATASHEET]  
9117I–AUTO–10/14  
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