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ATA556714N-DDB

更新时间： 2024-01-09 23:09:28
品牌 Logo 应用领域
爱特美尔 - ATMEL 电信集成电路电信电路射频异步传输模式ATM
页数 文件大小 规格书
36页 632K
描述
Multifunctional 330-bit Read/Write RF Identification IC

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ATA556714N-DDB 技术参数

生命周期：Obsolete包装说明：DIE,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
JESD-30 代码：R-XUUC-N功能数量：1
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：DIE
封装形状：RECTANGULAR封装形式：UNCASED CHIP
认证状态：Not Qualified表面贴装：YES
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子形式：NO LEAD端子位置：UPPER
Base Number Matches：1

ATA556714N-DDB 数据手册

 浏览型号ATA556714N-DDB的Datasheet PDF文件第3页浏览型号ATA556714N-DDB的Datasheet PDF文件第4页浏览型号ATA556714N-DDB的Datasheet PDF文件第5页浏览型号ATA556714N-DDB的Datasheet PDF文件第7页浏览型号ATA556714N-DDB的Datasheet PDF文件第8页浏览型号ATA556714N-DDB的Datasheet PDF文件第9页 
Figure 3-4. ATA5567 Traceability Data Structure  
Example:  
"E0"  
"15"  
"00"  
"41"  
8
1
...  
8
9
... 16 17 ... 24 25 ... 32  
Bit No.  
Block 1  
ACL  
MFC  
CID  
ICR  
LotID  
LSB  
63 MSB  
...  
...  
32  
0
Bit value  
31  
LotID  
Wafer #  
12 13 ... 17 18  
DW  
Block 2  
Bit No.  
1
...  
...  
31 32  
12  
20  
"557"  
ACL  
MFC  
UID  
Allocation class as defined in ISO/IEC 15963-1 = E0h  
Manufacturer code of Atmel Corporation as defined in ISO/IEC 7816-6 = 15h  
UID issuer identifier on request (respectively 5 bit CID and 3 bit ICR)  
Customer ID on request  
CID  
ICR  
IC revision  
LotID  
5-digit lot number, e.g., “41557”  
Wafer#  
DW  
5 bits for wafer#  
15 bits encoded as sequential die on wafer number  
4. Operating the ATA5567  
4.1  
Initialization and POR Delay  
The Power-On-Reset (POR) circuit remains active until an adequate voltage threshold has been  
reached. This threshold will be reached also if the coil voltage ramps up in terms of a few volts  
per second. It means that the tag can be moved slowly towards the reader without performance  
loss. This in turn triggers the default start-up delay sequence. During this configuration period of  
about 192 field clocks, the ATA5567 is initialized with the configuration data stored in EEPROM  
block 0. During initialization of the configuration block 0, for all ATA55670x variants the load  
damping is active permanently (see Figure 4-5 on page 10). The ATA55671x types (without  
damping option) achieve a longer read range based on the lower activation field strength.  
If the POR-delay bit is reset, no additional delay is observed after the configuration period. Tag  
modulation in regular-read mode will be observed about 3 ms after entering the RF field. If the  
POR delay bit is set, the ATA5567 remains in a permanent damping state until 8190 internal  
field clocks have elapsed.  
T
INIT = (192 + 8190 × POR delay) × TC ≈ 67 ms; TC = 8 µs at 125 kHz  
Any field gap occurring during this initialization phase will restart the complete sequence. After  
this initialization time the ATA5567 enters regular-read mode and modulation starts automati-  
cally using the parameters defined in the configuration register.  
6
ATA5567  
4874F–RFID–07/08  
1...3456789...36

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