ATA5558 [Preliminary]
2.2
2.3
Power-On Reset (POR) and Initialization
The Power-On-Reset circuit (POR) maintains the circuit in a reset state until an adequate inter-
nal operating voltage threshold level has been reached, whereupon a default start-up delay
sequence is started. During this period of 200 field clock cycles, the configuration and security
setup is initialized from the System Configuration and Page Security blocks.
Control Logic
The control logic is responsible for the following functions:
• Initialization and reloading of the configuration from EEPROM
• Control of read and write memory access operations
• Data transmission and command decoding
• CRC check, error detection and error handling
2.4
Modulator
The modulator output circuitry controls the switching of a resistive load between the Coil 1 and
Coil 2 pads to transmit data from the tag to the interrogator (uplink). The ASK load modulator is
driven from the Manchester, Bi-phase encoder or directly from the EEPROM memory data
stream (NRZ) according to the uplink encoding configuration.
Table 2-1.
Types of Modulation
Uplink Mode
Manchester Encoding
Bi-phase Encoding(1)
NRZ – Direct Data
ASK-coded
modulation
0 = falling edge on mid bit
1 = rising edge on mid bit
0 = rising or falling edge
1 = no edge on mid bit
1 = modulation off
0 = modulation on
Note:
1. Since Bi-phase encoding is data dependent the following definitions apply to the ATA5558
implementation.
- The tag modulates the first (half) bit period after SOF.
- If the last bit of a data stream is a logical 1 it is possible that this bit period is non-modu-
lated and therefore is not detectable directly by the reader.
Figure 2-1. Manchester Timing Diagram
1
Data rate = FRF/16
0
0
1
NRZ data stream
Manchester
coded Modulator
signal
Manchester coded
RF field
3
4681C–RFID–09/05