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AT91SAM9XE128_1 PDF预览

AT91SAM9XE128_1

更新时间: 2024-02-06 20:05:44
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
866页 12825K
描述
AT91 ARM Thumb Microcontrollers

AT91SAM9XE128_1 数据手册

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Features  
Incorporates the ARM926EJ-SARM® Thumb® Processor  
– DSP instruction Extensions, ARM Jazelle® Technology for Java® Acceleration  
– 8 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer  
– 200 MIPS at 180 MHz  
– Memory Management Unit  
– EmbeddedICE, Debug Communication Channel Support  
Additional Embedded Memories  
– One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed  
– One 32 Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16 Kbyte (for  
AT91SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed  
– 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128,  
AT91SAM9XE256 or AT91SAM9XE512 Respectively. Organized in 256, 512 or 1024  
Pages of 512 Bytes Respectively.  
AT91 ARM  
Thumb  
Microcontrollers  
• 128-bit Wide Access  
• Fast Read Time: 45 ns  
AT91SAM9XE128  
AT91SAM9XE256  
AT91SAM9XE512  
• Page Programming Time: 4 ms, Including Page Auto-erase,  
Full Erase Time: 10 ms  
• 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash  
Security Bit  
Enhanced Embedded Flash Controller (EEFC)  
– Interface of the Flash Block with the 32-bit Internal Bus  
– Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory  
Interface  
Preliminary  
External Bus Interface (EBI)  
– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash™  
USB 2.0 Full Speed (12 Mbits per second) Device Port  
– On-chip Transceiver, 2,688-byte Configurable Integrated DPRAM  
USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-pin PQFP Device  
and Double Port in 217-ball LFBGA Device  
– Single or Dual On-chip Transceivers  
– Integrated FIFOs and Dedicated DMA Channels  
Ethernet MAC 10/100 Base-T  
– Media Independent Interface or Reduced Media Independent Interface  
– 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit  
Image Sensor Interface  
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate  
– 12-bit Data Interface for Support of High Sensibility Sensors  
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format  
Bus Matrix  
– Six 32-bit-layer Matrix  
– Remap Command  
Fully-featured System Controller, including  
– Reset Controller, Shutdown Controller  
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes  
– Clock Generator and Power Management Controller  
– Advanced Interrupt Controller and Debug Unit  
– Periodic Interval Timer, Watchdog Timer and Real-time Timer  
6254B–ATARM–29-Apr-09  

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