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AT91SAM7X256B-CU PDF预览

AT91SAM7X256B-CU

更新时间: 2024-01-26 16:28:45
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器外围集成电路时钟
页数 文件大小 规格书
687页 10172K
描述
AT91 ARM Thumb-based Microcontrollers

AT91SAM7X256B-CU 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:TFBGA-100Reach Compliance Code:compliant
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.72Is Samacsys:N
具有ADC:YES地址总线宽度:
位大小:32最大时钟频率:50 MHz
DAC 通道:NODMA 通道:YES
外部数据总线宽度:JESD-30 代码:S-PBGA-B100
长度:9 mmI/O 线路数量:60
端子数量:100片上程序ROM宽度:8
最高工作温度:85 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
RAM(字节):65536ROM(单词):262144
ROM可编程性:FLASH座面最大高度:1.1 mm
速度:55 MHz最大供电电压:1.95 V
最小供电电压:1.65 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:9 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER, RISCBase Number Matches:1

AT91SAM7X256B-CU 数据手册

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Features  
Incorporates the ARM7TDMI® ARM® Thumb® Processor  
– High-performance 32-bit RISC Architecture  
– High-density 16-bit Instruction Set  
• Leader in MIPS/Watt  
– EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support  
Internal High-speed Flash  
– 512 Kbytes (AT91SAM7X512) Organized in Two Banks of 1024 Pages of  
256 Bytes (Dual Plane)  
AT91 ARM  
Thumb-based  
Microcontrollers  
– 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane)  
– 128 Kbytes (AT91SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane)  
• Single Cycle Access at Up to 30 MHz in Worst Case Conditions  
• Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed  
• Page Programming Time: 6 ms, Including Page Auto-erase,  
Full Erase Time: 15 ms  
• 10,000 Write Cycles, 10-year Data Retention Capability,  
Sector Lock Capabilities, Flash Security Bit  
AT91SAM7X512  
AT91SAM7X256  
AT91SAM7X128  
• Fast Flash Programming Interface for High Volume Production  
Internal High-speed SRAM, Single-cycle Access at Maximum Speed  
– 128 Kbytes (AT91SAM7X512)  
– 64 Kbytes (AT91SAM7X256)  
– 32 Kbytes (AT91SAM7X128)  
Memory Controller (MC)  
– Embedded Flash Controller, Abort Status and Misalignment Detection  
Reset Controller (RSTC)  
Preliminary  
– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout  
Detector  
– Provides External Reset Signal Shaping and Reset Source Status  
Clock Generator (CKGR)  
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL  
Power Management Controller (PMC)  
– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and  
Idle Mode  
– Four Programmable External Clock Signals  
Advanced Interrupt Controller (AIC)  
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources  
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt  
Protected  
Debug Unit (DBGU)  
– 2-wire UART and Support for Debug Communication Channel interrupt,  
Programmable ICE Access Prevention  
– Mode for General Purpose 2-wire UART Serial Communication  
Periodic Interval Timer (PIT)  
– 20-bit Programmable Counter plus 12-bit Interval Counter  
Windowed Watchdog (WDT)  
– 12-bit key-protected Programmable Counter  
– Provides Reset or Interrupt Signals to the System  
– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode  
6120H–ATARM–17-Feb-09  

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