AT91SAM7S256 Summary Preliminary
Block Diagram
Figure 1. AT91SAM7S256 Block Diagram
TDI
TDO
ICE
ARM7TDMI
Processor
JTAG
TMS
SCAN
TCK
JTAGSEL
1.8 V
Voltage
VDDIN
GND
System Controller
AIC
Regulator
VDDOUT
TST
FIQ
VDDCORE
VDDIO
IRQ0-IRQ1
Memory Controller
SRAM
Embedded
Address
Decoder
64 Kbytes
Flash
PCK0-PCK2
PLLRC
Controller
PLL
PMC
Abort
Status
Misalignment
Detection
XIN
XOUT
OSC
VDDFLASH
ERASE
Flash
RCOSC
256 Kbytes
VDDCORE
BOD
POR
Peripheral Bridge
Reset
Controller
VDDCORE
NRST
PGMRDY
Peripheral Data
Controller
PGMNVALID
PGMNOE
PGMCK
PGMM0-PGMM3
PGMD0-PGMD15
PGMNCMD
Fast Flash
Programming
Interface
11 Channels
PIT
WDT
RTT
APB
PGMEN0-PGMEN1
PDC
PDC
DRXD
DTXD
DBGU
FIFO
DDM
DDP
USB Device
PIOA
PWM0
PWM1
PWM2
PWM3
TF
TK
TD
RD
RK
RF
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DCD1
DSR1
DTR1
RI1
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
PDC
PWMC
USART0
PDC
PDC
PDC
SSC
PDC
USART1
Timer Counter
PDC
PDC
TC0
TC1
TC2
TWI
TIOA2
TIOB2
SPI
TWD
TWCK
PDC
PDC
ADTRG
AD0
AD1
AD2
AD3
ADC
AD4
AD5
AD6
AD7
ADVREF
3
6117AS–ATARM–20-Oct-04