Datasheet > AT89C51CC03C_14

AT89C51CC03C_14

更新时间： 2024-10-01 01:15:23

品牌	Logo	应用领域
爱特美尔 - ATMEL		PC
页数	文件大小	规格书
7页	114K
描述
PCA â Incorect Behavior with CPU X2 Mode Bit of HSB

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AT89C51CC03C_14 数据手册

Active Errata List

• CAN – Sporadic Errors

• PCA – Incorect Behavior with CPU X2 Mode Bit of HSB

• Timer0/1 – Extra Interrupt

• Transmission after a 3 bit Intermessage

Errata History

Lot Number

Errata List

1, 2, 3, 4

all lots from A02543

CAN

Microcontrollers

Errata Description

1. CAN – Sporadic Errors

When BRP = 0 or when BRP > 0 and SMP = 0, the CAN controller may desyn-

chronize and send one error frame to ask for the retransmission of the incoming

frame, even though it had no error.

AT89C51CC03

AT89C51CC03C

AT89C51CC03U

This is likely to occur with BRP = 0 or after long inter frame periods without syn-

chronization (low bus load). The CAN macro can still properly synchronize on

frames following the error.

Workaround

Setting BRP greater than 0 in CANBT1 and SMP equals 1 in CANBT3 allows re-

synchronization with the majority vote, and thus fixes the issue.

The sampling point might have to be slightly advanced for the majority vote to take

place within the bit. Therefore, at maximum speed of 1Mbit/s, the sampling point

should be at less than 80% (e.g. 75%) for XTAL = 16 MHz or less than 85% (e.g.

80%) for XTAL = 20 MHz.

Errata Sheet

2. PCA – Incorect Behavior with CPU X2 Mode Bit of HSB

When starting the microcontroller in X2 mode upon reset with the X2 fuse bit of

the HSB, the PCA may not work properly when configured with Timer0 in X1

mode as clock input.

Workaround

Set the CPU in X2 mode by software by writing CKCON register at the begin of

the application.

3. Timer0/1 – Extra Interrupt

When Timer0 is in X1 mode and Timer1 in X2 mode and vice versa, extra inter-

rupt may randomly occur for Timer0 or Timer1.

Workaround

Use the same mode for the two timers.

4. Transmission after a 3 bit Intermessage

If a Transmit Message Object (MOB) is enabled while the CAN bus is busy with

an on going message, the transmitter will wait for the 3-bit Intermission before

starting its transmission. This is in full agreement with the CAN recommendation.

4293G–CAN–06/05

12 3 4 5 6 7

中文翻译

下载PDF

与AT89C51CC03C_14相关器件

型号	品牌	获取价格	描述	数据表
AT89C51CC03C-7CTIM	ATMEL	获取价格	Enhanced 8-bit MCU with CAN Controller and Flash Memory
AT89C51CC03CA-7CTUM	ATMEL	获取价格	Enhanced 8-bit MCU with CAN Controller and Flash Memory
AT89C51CC03CA-RDTUM	ATMEL	获取价格	Enhanced 8-bit MCU with CAN Controller and Flash Memory
AT89C51CC03CA-RDTZM	ATMEL	获取价格	Enhanced 8-bit MCU with CAN Controller and Flash Memory
AT89C51CC03CA-RLTUM	ATMEL	获取价格	Enhanced 8-bit MCU with CAN Controller and Flash Memory
AT89C51CC03CA-RLTZM	ATMEL	获取价格	Enhanced 8-bit MCU with CAN Controller and Flash Memory
AT89C51CC03CA-S3SUM	ATMEL	获取价格	Enhanced 8-bit MCU with CAN Controller and Flash Memory
AT89C51CC03CA-SLSUM	ATMEL	获取价格	Enhanced 8-bit MCU with CAN Controller and Flash Memory
AT89C51CC03C-RDTIM	ATMEL	获取价格	Enhanced 8-bit MCU with CAN Controller and Flash Memory
AT89C51CC03C-RLTIM	ATMEL	获取价格	Enhanced 8-bit MCU with CAN Controller and Flash Memory

与AT89C51CC03C_14相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

29
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

23
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

25
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

35

产品中心

服务支持

精选活动

关于我们

帮助中心

AT89C51CC03C_14

AT89C51CC03C_14 数据手册

与AT89C51CC03C_14相关器件

与AT89C51CC03C_14相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AT89C51CC03C_14

AT89C51CC03C_14 数据手册

与AT89C51CC03C_14相关器件

与AT89C51CC03C_14相关文章

您还可以找

您在本页遇到什么问题？