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AT89C51CC03CA-7CTUM PDF预览

AT89C51CC03CA-7CTUM

更新时间： 2024-01-20 16:34:12
品牌 Logo 应用领域
爱特美尔 - ATMEL 闪存控制器
页数 文件大小 规格书
197页 2279K
描述
Enhanced 8-bit MCU with CAN Controller and Flash Memory

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AT89C51CC03CA-7CTUM 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LFBGA, BGA64,8X8,32针数：64
Reach Compliance Code：compliantECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.73
具有ADC：YES其他特性：ALSO OPERATES AT 3V SUPPLY
地址总线宽度：16位大小：8
CPU系列：8051最大时钟频率：40 MHz
DAC 通道：NODMA 通道：NO
外部数据总线宽度：8JESD-30 代码：S-PBGA-B64
JESD-609代码：e1长度：8 mm
I/O 线路数量：37端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
PWM 通道：YES封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA64,8X8,32
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3/5 V
认证状态：Not QualifiedRAM（字节）：256
ROM（单词）：65536ROM可编程性：FLASH
座面最大高度：1.5 mm速度：60 MHz
子类别：Microcontrollers最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
宽度：8 mmuPs/uCs/外围集成电路类型：MICROCONTROLLER
Base Number Matches：1

AT89C51CC03CA-7CTUM 数据手册

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Features  
• 80C51 Core Architecture  
• 256 Bytes of On-chip RAM  
• 2048 Bytes of On-chip ERAM  
• 64K Bytes of On-chip Flash Memory  
– Data Retention: 10 Years at 85°C  
– Read/Write Cycle: 100K  
• 2K Bytes of On-chip Flash for Bootloader  
• 2K Bytes of On-chip EEPROM  
Read/Write Cycle: 100K  
• Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply  
• 14-sources 4-level Interrupts  
• Three 16-bit Timers/Counters  
• Full Duplex UART Compatible 80C51  
• High-speed Architecture  
Enhanced 8-bit  
MCU with CAN  
Controller and  
Flash Memory  
– In Standard Mode:  
40 MHz (Vcc 3V to 5.5V, both Internal and external code execution)  
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)  
– In X2 mode (6 Clocks/machine cycle)  
20 MHz (Vcc 3V to 5.5V, both Internal and external code execution)  
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)  
• Five Ports: 32 + 4 Digital I/O Lines  
AT89C51CC03  
• Five-channel 16-bit PCA with  
– PWM (8-bit)  
– High-speed Output  
– Timer and Edge Capture  
• Double Data Pointer  
• 21-bit WatchDog Timer (7 Programmable Bits)  
• A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs  
• SPI Interface, (PLCC52, VPFP64 and CABGA 64 packages only)  
• Full CAN Controller  
– Fully Compliant with CAN Rev 2.0A and 2.0B  
– Optimized Structure for Communication Management (Via SFR)  
– 15 Independent Message Objects  
– Each Message Object Programmable on Transmission or Reception  
– Individual Tag and Mask Filters up to 29-bit Identifier/Channel  
– 8-byte Cyclic Data Register (FIFO)/Message Object  
– 16-bit Status and Control Register/Message Object  
– 16-bit Time-Stamping Register/Message Object  
– CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message  
Object  
– Access to Message Object Control and Data Registers Via SFR  
– Programmable Reception Buffer Length Up To 15 Message Objects  
– Priority Management of Reception of Hits on Several Message Objects at the  
Same Time (Basic CAN Feature)  
– Priority Management for Transmission  
– Message Object Overrun Interrupt  
– Supports  
– Time Triggered Communication  
– Autobaud and Listening Mode  
– Programmable Automatic Reply Mode  
– 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode  
– Readable Error Counters  
– Programmable Link to On-chip Timer for Time Stamping and Network  
Synchronization  
– Independent Baud Rate Prescaler  
– Data, Remote, Error and Overload Frame Handling  
Rev. 4182K–CAN–05/06  
1.  
At BRP = 1 sampling point will be fixed.  
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