Datasheet > AT88SC0104C-09NT-XX-2.7

AT88SC0104C-09NT-XX-2.7

更新时间： 2024-02-09 14:05:12

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程只读存储器电动程控只读存储器电可擦编程只读存储器 ATM 异步传输模式
页数	文件大小	规格书
13页	141K
描述
EEPROM,

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AT88SC0104C-09NT-XX-2.7 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.61
Base Number Matches：	1

AT88SC0104C-09NT-XX-2.7 数据手册

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AT88SC0104C

Protocol Selection

The AT88SC0104C is compatible with two different communication protocols: asynchro-

nous T = 0 as defined by ISO 7816-3 or synchronous two-wire protocol. The power-up

sequence determines which of the two protocols will be used.

Asynchronous

T = 0 Protocol

The power-up sequence complies with ISO 7816-3 for a cold reset.

•

V_CCgoes high; RST, I/O-SDA and CLK-SCL are low.

Set I/O-SDA in receive mode.

Provide a clock signal to CLK-SCL.

RST goes high after 400 clock cycles.

The device will respond with a 64-bit ATR code, including historical bytes to indicate the

memory density within the CryptoMemory family. Once the asynchronous mode has

been selected, it is not possible to switch to the synchronous mode without powering off

the device.

Figure 2. Asynchronous T = 0 Protocol

ATR

I/O-SDA

RST

CLK-SCL

Synchronous

Two-wire Protocol

The synchronous mode is the default after powering up V_CCdue to the internal pull-up

on RST.

•

Power-up V_CC, RST goes high also.

After stable V_CC, CLK-SCL and I/O-SDA may be driven.

Figure 3. Synchronous Two-wire Protocol

I/O-SDA

RST

CLK-SCL

Note:

Four clock pulses must be sent before the first command is issued.

2021BS–SMEM–10/02

1 2 3 456 7 8...13

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