3.
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other condition beyond those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect
device reliability.
Operating temperature..................−40° C to +85° C
Storage temperature .................−65° C to + 150° C
Voltage on any pin
with respect to ground ................− 0.5 to VCC+0.5 V
4.
AC Parameters
Table 4-1. AC Parameters
Parameter
Symbol
Direction
Min
Typ
Max
Unit Notes
Signal can be stable in either high or low levels
Wake low
duration
tWLO
To AT88SA10HS
60
-
µs
during extended sleep intervals
Wake delay to
data comm.
tWHI
To AT88SA10HS
2.5
45
ms Signal should be stable high for this entire
duration. tWHI must not exceed tTIMEOUT or the chip
will transition to sleep
Start pulse
duration
t START
To AT88SA10HS
4.1
4.6
4.34
6.0
4.56
8.6
µs
µs
From
AT88SA10HS
Zero
transmission
high pulse
t ZHI
t ZLO
t BIT
To AT88SA10HS
4.1
4.6
4.34
6.0
4.56
8.6
µs
µs
From
AT88SA10HS
Zero
transmission low
pulse
To AT88SA10HS
4.1
4.6
4.34
6.0
4.56
8.6
µs
µs
From
AT88SA10HS
Bit time‡
To AT88SA10HS
37
39
-
If the bit time exceeds tTIMEOUT then AT88SA10HS
will enter sleep mode and the Wake token must
be resent
µs
From
AT88SA10HS
41
28
54
60
78
95
µs
Turn around
delay
t TURNAROUND
From
AT88SA10HS will initiate the first low going
transition after this time interval following the end
of the Transmit flag
µs
AT88SA10HS
To AT88SA10HS
To AT88SA10HS
45ms
After AT88SA10HS transmits the last bit of a
block, system must wait this interval before
sending the first bit of a flag
15µs
High side glitch
filter @ active
t HIGNORE_A
45
ns
Pulses shorter than this in width will be ignored by
the chip, regardless of its state when active
Low side glitch
filter @ active
t LIGNORE_A
t LIGNORE_S
t TIMEOUT
To AT88SA10HS
To AT88SA10HS
45
ns
ns
Pulses shorter than this in width will be ignored by
the chip, regardless of its state when active
Low side glitch
filter @ sleep
500
Pulses shorter than this in width will be ignored by
the chip when in sleep mode
IO Timeout
To AT88SA10HS
To AT88SA10HS
45
3
65
4
85
ms See Section 5.4.1
Max. time from Wake until chip is forced into sleep
mode. See Section 5.5
Watchdog reset tWATCHDOG
5.7
s
Pause Length t PAUSE
-
18
25
32
ms Duration during which the chip will ignore IO on
the bus. See PauseShort command, Section 6.7
Atmel AT88SA10HS [DATASHEET]
6
8595G−CRYPTO−9/11
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