Datasheet > 微控制器和处理器 > 其他 uPs/uCs/外围集成电路> AT83C24B-PRRUL

AT83C24B-PRRUL

更新时间： 2024-02-23 21:38:03

品牌	Logo	应用领域
爱特美尔 - ATMEL		微控制器和处理器外围集成电路 uCs集成电路 uPs集成电路异步传输模式 ATM
页数	文件大小	规格书
42页	551K
描述
Smart Card Reader Interface with Power Management

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技术参数
数据手册

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AT83C24B-PRRUL 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	SOP, SOP28,.56	Reach Compliance Code：	compliant
风险等级：	5.08	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	湿度敏感等级：	3
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP28,.56
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3/5 V	认证状态：	Not Qualified
子类别：	Other Microprocessor ICs	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

AT83C24B-PRRUL 数据手册

AT83C24

Read Command

After the slave address has been configured, the read command allows to read one or several

bytes in the following order:

•

STATUS, CONFIG0, CONFIG1, CONFIG2, CONFIG3, INTERFACE, TIMER1, TIMER0,

CAPTURE1, CAPTURE0

•

FFh is completing the transfer if the microcontroller attempts to read beyond the last byte.

Note:

Flags are only reset after the corresponding byte read has been acknowledged by the master.

Table 4. Read Command Description

Byte Description

Address byte

Data byte 1

Data byte 2

Data byte 3

Data byte 4

Data byte 5

Data byte 6

Data byte 7

Data byte 8

Data byte 9

Data byte 10

Data byte 11

Data byte 12

Byte Value

0100 A₂A₁A₀1

STATUS

CONFIG0

CONFIG1

CONFIG2

CONFIG3

CONFIG4

INTERFACE

TIMER 1 (MSB)

TIMER 0 (LSB)

CAPTURE 1 (MSB)

CAPTURE 0 (LSB)

0xFF

Interrupts

The PRES/INT behavior depends on IT_SEL bit value (see CONFIG4 register).

•

If IT_SEL= 0, the PRES/INT output is High by default (on chip pull up or open drain).

PRES/INT is driven Low by any of the following event:

–

INSERT bit set in CONFIG0 register (card insertion/extraction or bit set by software )

VCARD_INT bit set in STATUS register (the DC/DC output voltage has settled)

over-current detection on CVCC

VCARDERR bit set in CONFIG0 register (out of range voltage on CVCC or bit set by

software)

–

ATRERR bit set in CONFIG0 register (no ATR before the card clock counter

overflows or bit set by software).This control of ATR timing is only available if ART bit

=1.

If IT_SEL=0, a read command of STATUS register and of CONFIG0 register will release

PRES/INT pin to high level.

Several AT83C24 devices can share the same interrupt and the microcontroller can identify

the interrupt sources by polling the status of the AT83C24 devices using TWI commands.

•

If IT_SEL= 1 (mandatory for NDS applications and for software compatibility with existing

devices) the PRES/INT output is High to indicate a card is present and none of the following

event has occured:

4234F–SCR–10/05

1...6 7 8910 11 12...42

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与AT83C24B-PRRUL相关器件

型号	品牌	描述	获取价格	数据表
AT83C24B-PRRUM	ATMEL	Smart Card Reader Interface with Power Management	获取价格
AT83C24B-PRTIL	ATMEL	Smart Card Reader Interface with Power Management	获取价格
AT83C24B-PRTIM	ATMEL	Smart Card Reader Interface with Power Management	获取价格
AT83C24B-PRTUL	ATMEL	Smart Card Reader Interface with Power Management	获取价格
AT83C24B-PRTUM	ATMEL	Smart Card Reader Interface with Power Management	获取价格
AT83C24B-TIRIL	ATMEL	Smart Card Reader Interface with Power Management	获取价格

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