EEPROM
AS8E128K32
Austin Semiconductor, Inc.
of the last byte written will result in the complement of the written
data to be presented on I/O7. Once the write cycle has been com-
pleted, true data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write cycle.
DEVICE IDENTIFICATION
An extra 128 bytes of EEPROM memory is available on each
die for user identification. By raising A9 to 12V + 0.5V and using
address locations 1FF80H to 1FFFFH the bytes may be written to
or read from in the same manner as the regular memory array.
TOGGLE BIT
In addition to DATAPolling the module provides another method
for determining the end of a write cycle. During the write operation,
successive attempts to read data from the device will result in I/O6 of
the accessed die toggling between one and zero. Once the write has
completed, I/O6 will stop toggling and valid data will be read. Reading
the toggle bit may begin at any time during the write cycle.
DEVICE OPERATION
The 128K x 32 EEPROM memory solution is an electrically
erasable and programmable memory module that is accessed like a
Static RAM for the read or write cycle without the need for external
components. The device contains a 128-byte-page register to allow
writing of up to 128 bytes of data simultaneously. During a write
cycle, the address and 1 to 128 bytes of data are internally latched,
freeing the address and data bus for other operations. Following the DATA PROTECTION
initiation of a write cycle, the device will automatically write the
latched data using an internal control timer. The end of a write cycle
can be detected by DATA polling of I/O7. Once the end of a write
cycle has been detected a new access for a read or write can begin.
If precautions are not taken, inadvertent writes may occur during
transitions of the host power supply. The E2 module has incorpo-
rated both hardware and software features that will protect the memory
against inadvertent writes.
READ
HARDWARE PROTECTION
The memory module is accessed like a Static RAM. When CE\
and OE\ are low and WE\ is High, the data stored at the memory
location determined by the address pins is asserted on the outputs.
The module can be read as a 32 bit, 16 bit or 8 bit device. The outputs
are put in the high impedance state when either CE\ or OE\ is high.
This dual-line control gives designers flexibility in preventing bus
contention in their system.
Hardware features protect against inadvertent writes to the mod-
ule in the following ways: (a) Vcc sense - if Vcc is below 3.8 V
(typical) the write function is inhibited; (b) Vcc power-on delay -
once Vcc has reached 3.8 V the device will automatically time out 5 ms
(typical) before allowing a write; (c) write inhibit - holding any one of
OE\ low, CE\ high or WE\ high inhibits write cycles; (d) noise filter -
pulses of less than 15 ns (typical) on the WE\ or CE\ inputs will not
initiate a write cycle.
BYTEWRITE
A low pulse on the WE\ or CE\ input with CE\ or WE\ low
(respectively) and OE\ high initiates a write cycle. The address is
latched on the falling edge of CE\ or WE\, whichever occurs last. The
data is latched by the first rising edge of CE\ or WE\. Once a BWDW
(byte, word or double word) write has been started it will automati-
cally time itself to completion.
SOFTWARE DATA PROTECTION
A software controlled data protection feature has been imple-
mented on the memory module. When enabled, the software data
protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user and is shipped with SDP
disabled, SDP is enabled by the host system issuing a series of three
write commands; three specific bytes of data are written to three
specific addresses (refer to Software Data Protection Algorithm). After
writing the three byte command sequence and after tWC the entire
module will be protected from inadvertent write operations. It should
be noted, that once protected the host may still perform a byte of page
write to the module. This is done by preceding the data to be written
by the same three byte command sequence used to enable SDP. Once
set, SDP will remain active unless the disable command sequence is
issued. Power transitions do not disable SDP and SDP will protect
the 128K x 32 EEPROM during power-up and Power-down condi-
tions. All command sequences must conform to the page write timing
specifications. The data in the enable and disable command sequences
is not written to the device and the memory addresses used in the
sequence may be written with data in either a byte or page write
operation.
PAGEWRITE
The page write operation of the 128K x 32 EEPROM allows 1 to
128 BWDWs of data to be written into the device during a single
internal programming period. Each new BWDW must be written
within 150-µ sec (tBLC) of the previous BWDW. If the tBLC limit is
exceeded the memory module will cease accepting data and commence
the internal programming operation. For each WE high to low transi-
tion during the page write operation, A7-A16 must be the same.
The A0-A6 inputs are used to specify which bytes within the
page are to be written. The bytes may be loaded in any order and may
be altered within the same load period. Only bytes which are speci-
fied for writing will be written; unnecessary cycling of other bytes
within the page does not occur.
After setting SDP, any attempt to write to the device without the
three byte command sequence will start the internal write timers. No
DATA POLLING
This memory module features DATA Polling to indicate the end
of a write cycle. During a byte or page write cycle an attempted read
data will be written to the device; however, for the duration of tWC
read operations will effectively be polling operations.
,
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8E128K32
Rev. 7.6 06/05
2
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