5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> AS7C33512PFS36A-166TQC
AS7C33512PFS36A-166TQC PDF预览

AS7C33512PFS36A-166TQC

更新时间： 2024-01-14 10:25:33
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
19页 542K
描述
3.3V 512K x 32/36 pipelined burst synchronous SRAM

阅读下载

中文翻译

获取价格

AS7C33512PFS36A-166TQC 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.51最长访问时间：3.4 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：166 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：18874368 bit内存集成电路类型：STANDARD SRAM
内存宽度：36功能数量：1
端子数量：100字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

AS7C33512PFS36A-166TQC 数据手册

 浏览型号AS7C33512PFS36A-166TQC的Datasheet PDF文件第2页浏览型号AS7C33512PFS36A-166TQC的Datasheet PDF文件第3页浏览型号AS7C33512PFS36A-166TQC的Datasheet PDF文件第4页浏览型号AS7C33512PFS36A-166TQC的Datasheet PDF文件第6页浏览型号AS7C33512PFS36A-166TQC的Datasheet PDF文件第7页浏览型号AS7C33512PFS36A-166TQC的Datasheet PDF文件第8页 
AS7C33512PFS32A  
AS7C33512PFS36A  
®
Signal descriptions  
Description  
Pin  
CLK  
I/O Properties  
I
I
CLOCK  
SYNC  
SYNC  
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.  
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.  
Data. Driven as output when the chip is enabled and when OE is active.  
A,A0,A1  
DQ[a,b,c,d]  
I/O  
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,  
ADSP is blocked. Refer to the “Synchronous truth table” for more information.  
CE0  
I
I
SYNC  
SYNC  
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when  
ADSC is active or when CE0 and ADSP are active.  
CE1, CE2  
ADSP  
ADSC  
ADV  
I
I
I
SYNC  
SYNC  
SYNC  
Address strobe processor. Asserted low to load a new address or to enter standby mode.  
Address strobe controller. Asserted low to load a new address or to enter standby mode.  
Advance. Asserted low to continue burst read/write.  
Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and BW[a:d]  
control write enable.  
GWE  
BWE  
I
I
SYNC  
SYNC  
Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.  
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of  
BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive,  
the cycle is a read cycle.  
BW[a,b,c,d]  
I
SYNC  
OE  
I
I
ASYNC  
STATIC  
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.  
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When  
driven Low, device follows linear Burst order. This signal is internally pulled High.  
LBO  
ZZ  
I
-
ASYNC  
-
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.  
No connect  
NC  
Snooze Mode  
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of  
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.  
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.  
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is  
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.  
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting  
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.  
12/23/04, v 2.6  
Alliance Semiconductor  
5 of 19  
12345678...19

中文翻译

下载PDF

与AS7C33512PFS36A-166TQC相关器件

型号 品牌 获取价格 描述 数据表
AS7C33512PFS36A-166TQCN ALSC

获取价格

 		3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFS36A-166TQI ALSC

获取价格

 		3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFS36A-166TQIN ALSC

获取价格

 		3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFS36A-225BC ALSC

获取价格

 		Standard SRAM, 512KX36, 6.9ns, CMOS, PBGA165, BGA-165
AS7C33512PFS36A-225BI ALSC

获取价格

 		Standard SRAM, 512KX36, 6.9ns, CMOS, PBGA165, BGA-165
AS7C33512PFS36A-225TQC ALSC

获取价格

 		Standard SRAM, 512KX36, 6.9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C33512PFS36A-225TQI ALSC

获取价格

 		Standard SRAM, 512KX36, 6.9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C33512PFS36A-250BC ALSC

获取价格

 		Standard SRAM, 512KX36, 6.5ns, CMOS, PBGA165, BGA-165
AS7C33512PFS36A-250TQC ALSC

获取价格

 		Standard SRAM, 512KX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C3364FT32B ALSC

获取价格

 		3.3V 64K x 32/36 Flow Through Synchronous SRAM

与AS7C33512PFS36A-166TQC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证