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AS7C33512PFS36A-166TQC PDF预览

AS7C33512PFS36A-166TQC

更新时间： 2024-01-23 07:18:17
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
19页 542K
描述
3.3V 512K x 32/36 pipelined burst synchronous SRAM

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中文翻译

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AS7C33512PFS36A-166TQC 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.51最长访问时间：3.4 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：166 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：18874368 bit内存集成电路类型：STANDARD SRAM
内存宽度：36功能数量：1
端子数量：100字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

AS7C33512PFS36A-166TQC 数据手册

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AS7C33512PFS32A  
AS7C33512PFS36A  
®
Functional description  
The AS7C33512PFS32A/36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device  
organized as 524,288 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any given technology.  
Fast cycle times of 6/7.5 ns with clock access times (tCD) of 3.4/3.8 ns enable 166, and 133 MHz bus frequencies. Three chip enable (CE)  
inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor  
address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.  
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register  
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data  
accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out registers and driven  
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all  
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address  
strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved  
count sequence. With LBO driven low, the device uses a linear count sequence.  
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/  
36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE  
and the appropriate individual byte BWn signals.  
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when  
BWn is sampled lOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented  
internally to the next burst address if BWn and ADV are sampled low. This device operates in single-cycle deselect feature during read  
cycles.  
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are  
as follows:  
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.  
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).  
• Master chip enable CE0 blocks ADSP, but not ADSC.  
The AS7C33512PFS32A/36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or  
3.3V. These devices are available in a 100-pin TQFP package.  
TQFP capacitance  
Parameter  
Input capacitance  
I/O capacitance  
Symbol  
Test conditions  
VIN = 0V  
Min  
Max  
Unit  
pF  
*
CIN  
-
-
5
7
*
CI/O  
VOUT = 0V  
pF  
* Guaranteed not tested  
TQFP thermal resistance  
Description  
Conditions  
Symbol  
θJA  
Typical  
40  
Units  
°C/W  
°C/W  
1–layer  
4–layer  
Thermal resistance  
(junction to ambient)1  
Test conditions follow standard test methods  
and procedures for measuring thermal  
impedance, per EIA/JESD51  
θJA  
22  
Thermal resistance  
(junction to top of case)1  
θJC  
8
°C/W  
1 This parameter is sampled  
12/23/04, v 2.6  
Alliance Semiconductor  
4 of 19  
1234567...19

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与AS7C33512PFS36A-166TQC相关器件

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AS7C33512PFS36A-166TQCN ALSC

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 		3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFS36A-166TQI ALSC

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 		3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFS36A-166TQIN ALSC

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 		3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFS36A-225BC ALSC

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 		Standard SRAM, 512KX36, 6.9ns, CMOS, PBGA165, BGA-165
AS7C33512PFS36A-225BI ALSC

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 		Standard SRAM, 512KX36, 6.9ns, CMOS, PBGA165, BGA-165
AS7C33512PFS36A-225TQC ALSC

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 		Standard SRAM, 512KX36, 6.9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C33512PFS36A-225TQI ALSC

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 		Standard SRAM, 512KX36, 6.9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C33512PFS36A-250BC ALSC

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 		Standard SRAM, 512KX36, 6.5ns, CMOS, PBGA165, BGA-165
AS7C33512PFS36A-250TQC ALSC

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 		Standard SRAM, 512KX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C3364FT32B ALSC

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 		3.3V 64K x 32/36 Flow Through Synchronous SRAM

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