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AS7C33512PFD32A-166BCN PDF预览

AS7C33512PFD32A-166BCN

更新时间： 2024-02-24 04:57:33
品牌 Logo 应用领域
ALSC ISM频段静态存储器内存集成电路
页数 文件大小 规格书
23页 600K
描述
Standard SRAM, 512KX32, 3.4ns, CMOS, PBGA165, LEAD FREE, BGA-165

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AS7C33512PFD32A-166BCN 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：TBGA, BGA165,11X15,40
针数：165Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.79最长访问时间：3.4 ns
其他特性：PIPELINED ARCHITECTUREI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e3/e6
长度：15 mm内存密度：16777216 bit
内存集成电路类型：STANDARD SRAM内存宽度：32
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.04 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：PURE MATTE TIN/TIN BISMUTH
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：40
宽度：13 mmBase Number Matches：1

AS7C33512PFD32A-166BCN 数据手册

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AS7C33512PFD32A  
AS7C33512PFD36A  
®
Signal descriptions  
Description  
Pin  
CLK  
I/O Properties  
I
I
CLOCK  
SYNC  
SYNC  
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.  
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.  
Data. Driven as output when the chip is enabled and when OE is active.  
A,A0,A1  
DQ[a,b,c,d]  
I/O  
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,  
ADSP is blocked. Refer to the “Synchronous truth table” for more information.  
CE0  
I
I
SYNC  
SYNC  
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when  
ADSC is active or when CE0 and ADSP are active.  
CE1, CE2  
ADSP  
ADSC  
ADV  
I
I
I
SYNC  
SYNC  
SYNC  
Address strobe processor. Asserted low to load a new address or to enter standby mode.  
Address strobe controller. Asserted low to load a new address or to enter standby mode.  
Advance. Asserted low to continue burst read/write.  
Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and BW[a:d]  
control write enable.  
GWE  
BWE  
I
I
SYNC  
SYNC  
Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.  
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of  
BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive,  
the cycle is a read cycle.  
BW[a,b,c,d]  
I
SYNC  
OE  
I
I
ASYNC  
STATIC  
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.  
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When  
driven Low, device follows linear Burst order. This signal is internally pulled High.  
LBO  
TDO  
TDI  
O
I
SYNC  
SYNC  
SYNC  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).  
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).  
TMS  
I
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA only).  
Test Clock. All inputs are sampled on the rising edge of TCK. All outputs are driven from the falling  
edge of TCK.  
TCK  
I
Test Clock  
ZZ  
I
-
ASYNC  
-
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.  
No connects  
NC  
Write enable truth table (per byte)  
Function  
GWE BWE  
BWa  
X
BWb  
X
BWc  
X
BWd  
X
L
H
H
H
H
H
X
L
L
L
H
L
Write All Bytes  
L
L
L
L
Write Byte a  
L
H
H
H
Write Byte c and d  
H
H
L
L
X
X
X
X
Read  
H
H
H
H
Key: X = don’t care, L = low, H = high, n = a, b, c, d; BWE, BWn = internal write signal.  
4/12/04, v.1.0  
Alliance Semiconductor  
5 of 23  
12345678...23

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AS7C33512PFD32A-166BIN ALSC

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AS7C33512PFD32A-166TQC ALSC

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 		3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD32A-166TQCN ALSC

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 		3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD32A-166TQI ALSC

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 		3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD32A-166TQIN ALSC

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 		3.3V 512K x 32/36 pipelined burst synchronous SRAM
AS7C33512PFD32A-200BC ALSC

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 		Standard SRAM, 512KX32, 3ns, CMOS, PBGA119, BGA-119
AS7C33512PFD32A-200BI ALSC

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 		Standard SRAM, 512KX32, 3ns, CMOS, PBGA119, BGA-119
AS7C33512PFD32A-200TQC ALSC

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 		Standard SRAM, 512KX32, 3ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C33512PFD32A-200TQI ALSC

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 		Standard SRAM, 512KX32, 3ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C33512PFD36A-100BC ALSC

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 		Standard SRAM, 512KX36, 4ns, CMOS, PBGA119, BGA-119

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