Datasheet > AS7C251MNTD36A-200BC

AS7C251MNTD36A-200BC

更新时间： 2024-01-07 06:59:03

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
22页	453K
描述
ZBT SRAM, 1MX36, 6.5ns, CMOS, PBGA165, BGA-165

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AS7C251MNTD32A

AS7C251MNTD36A

Functional description

The AS7C251MNTD32A/36A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM)

organized as 1,048,576 words × 32 or 36 bits and incorporates a LATE LATE Write.

This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Delay (NTD^™) architecture, featuring an enhanced write

operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address

are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead'

cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random

access or read-modify-write operations.

NTD^™devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle

flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With

NTD^™, write and read operations can be used in any order without producing dead bus cycles.

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes.

Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock

cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for

normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined

mode, a two cycle deselect latency allows pending read or write operations to be completed.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W

pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including

burst, can be stalled using the CEN=1, the clock enable input.

The AS7C251MNTD32A/36A operates with a 2.5V ± 5% power supply for the device core (V_DD). These devices are available in a 100-pin

TQFP and 165-ball BGA packages.

Capacitance

Parameter

Symbol

Test conditions

V = 0V

Min

Max

Unit

Input capacitance

I/O capacitance

V = V = 0V

I/O

out

TQFP and BGA thermal resistance

Description

Conditions

Symbol

Typical

Units

°C/W

1–layer

4–layer

θ_JA

Thermal resistance

(junction to ambient)¹

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51

Thermal resistance

(junction to top of case)¹

θ_JC

°C/W

1 This parameter is sampled

4/26/04, V 1.0

Alliance Semiconductor

P. 4 of 22

1 2 345 6 7...22

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与AS7C251MNTD36A-200BC相关器件

型号	品牌	获取价格	描述	数据表
AS7C251MNTD36A-200BCN	ALSC	获取价格	ZBT SRAM, 1MX36, 6.5ns, CMOS, PBGA165, LEAD-FREE, BGA-165
AS7C251MNTD36A-200BI	ALSC	获取价格	ZBT SRAM, 1MX36, 6.5ns, CMOS, PBGA165, BGA-165
AS7C251MNTD36A-200BIN	ALSC	获取价格	ZBT SRAM, 1MX36, 6.5ns, CMOS, PBGA165, LEAD-FREE, BGA-165
AS7C251MNTD36A-200TQC	ALSC	获取价格	2.5V 1M x 32/36 Pipelined SRAM with NTD
AS7C251MNTD36A-200TQC	ISSI	获取价格	ZBT SRAM, 1MX36, 3.2ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C251MNTD36A-200TQCN	ALSC	获取价格	2.5V 1M x 32/36 Pipelined SRAM with NTD
AS7C251MNTD36A-200TQI	ALSC	获取价格	2.5V 1M x 32/36 Pipelined SRAM with NTD
AS7C251MNTD36A-200TQIN	ALSC	获取价格	2.5V 1M x 32/36 Pipelined SRAM with NTD
AS7C251MNTF18A	ALSC	获取价格	2.5V 1M x 18 Flowthrough Synchronous SRAM with NTD
AS7C251MNTF18A-10TQC	ALSC	获取价格	2.5V 1M x 18 Flowthrough Synchronous SRAM with NTD

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