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AS4LC4M4E0-60TC PDF预览

AS4LC4M4E0-60TC

更新时间： 2024-01-11 17:43:40
品牌 Logo 应用领域
其他 - ETC 内存集成电路光电二极管动态存储器
页数 文件大小 规格书
15页 266K
描述
x4 EDO Page Mode DRAM

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AS4LC4M4E0-60TC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP包装说明：SOP, TSOP24/26,.36
针数：26/24Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.02
风险等级：5.81Is Samacsys：N
访问模式：FAST PAGE WITH EDO最长访问时间：60 ns
其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESHI/O 类型：COMMON
JESD-30 代码：R-PDSO-G24JESD-609代码：e0
内存密度：16777216 bit内存集成电路类型：EDO DRAM
内存宽度：4功能数量：1
端口数量：1端子数量：24
字数：4194304 words字数代码：4000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：4MX4
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：TSOP24/26,.36
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：240电源：3.3 V
认证状态：Not Qualified刷新周期：4096
自我刷新：YES最大待机电流：0.001 A
子类别：DRAMs最大压摆率：0.11 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

AS4LC4M4E0-60TC 数据手册

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AS4LC4M4E0  
AS4LC4M4E1  
®
Functional description  
The AS4LC4M4E0 and AS4LC4M4E1 are high performance 16-megabit CMOS Dynamic Random Access Memories (DRAM) organized as  
4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high  
speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for  
use as main memory in PC, workstation, router and switch applications.  
These products feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at  
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the  
falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of  
column addresses prior to CAS assertion.  
Extended data out (EDO) read mode enables 60MHz operation using 60ns devices. In contrast to 'fast page mode' devices, data remains active  
on outputs after CAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and  
prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of  
RAS and CAS going high.  
Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:  
•
RAS-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.  
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with  
previous valid data.  
•
CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.  
Outputs are high-impedence (OE and WE are don't care).  
• Normal read or write cycles refresh the row being accessed.  
• Self-refresh cycles  
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:  
•
RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.  
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with  
previous valid data.  
•
CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.  
Outputs are high-impedence (OE and WE are don't care).  
• Normal read or write cycles refresh the row being accessed.  
• Self-refresh cycles  
The AS4LC4M4E0 and AS4LC4M4E1 are available in the standard 24/26-pin plastic SOJ and 24/26-pin plastic TSOP packages. The  
AS4LC4M4E0 and AS4LC4M4E1 operate with a single power supply of 3V 0.3V. All provide TTL compatible inputs and outputs.  
4/11/01; V.1.1  
Alliance Semiconductor  
P. 2 of 15  
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