Datasheet > AS4C64M16D3L-12BIN

AS4C64M16D3L-12BIN

更新时间： 2022-02-26 14:10:54

品牌	Logo	应用领域
ALSC		/
页数	文件大小	规格书
90页	2173K
描述
JEDEC Standard Compliant

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1Gb DDR3L – AS4C64M16D3L

LDM,

UDM

Input

Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle.

LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.

DQ0 - DQ15 Input /

Output

Data I/O: The data bus input and output data are synchronized with positive and negative

edges of DQS/DQS#. The I/Os are byte-maskable during Writes.

ODT

Input

On Die Termination: ODT (registered HIGH) enables termination resistance internal to

the DDR3L SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS#. The ODT

pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT.

RESET#

Input

Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive

when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a

CMOS rail to rail signal with DC high and low at 80% and 20% of VDD

V_DD

V_SS

Supply

Power Supply: 1.35V -0.067V/+0.1V.

Ground

V_DDQ

V_SSQ

V_REFCA

V_REFDQ

DQ Power: 1.35V -0.067V/+0.1V.

DQ Ground

Supply Reference voltage for CA

Supply Reference voltage for DQ

Supply Reference pin for ZQ calibration.

No Connect: These pins should be left unconnected.

Confidential

Rev. 2.0

Aug. /2014

1...4 5 678 9 10...90

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