Datasheet > AS4C2M32SA

AS4C2M32SA

更新时间： 2022-02-26 11:39:35

品牌	Logo	应用领域
ALSC		动态存储器
页数	文件大小	规格书
54页	5692K
描述
64Mb SDRAM AS4C2M32SA - 86pin TSOP II PACKAGE

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数据手册

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AS4C2M32SA 数据手册

AS4C2M32SA-6TIN

AS4C2M32SA-6TCN

AS4C2M32SA-7TCN

Figure 4. Burst Read Operation

(Burst Length = 4, CAS# Latency = 2, 3)

T3 T4 T5 T6 T7 T8

CLK

NOP

READ A

NOP

COMMAND

CAS# latency=2

t_CK2,DQ

DOUT A₀DOUT A₁DOUT A₂DOUT A₃

CAS# latency=3

t_CK3,DQ

DOUT A₀DOUT A₁DOUT A₂DOUT A₃

The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.

DQM latency is two clocks for output buffers). A read burst without the auto precharge function may be

interrupted by a subsequent Read or Write command to the same bank or the other active bank before

the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the

same bank too. The interrupt coming from the Read command can occur on any clock cycle following a

previous Read command (refer to the following figure).

Figure 5. Read Interrupted by a Read

(Burst Length = 4, CAS# Latency = 2, 3)

CLK

COMMAND

READ A

NOP

READ B

CAS# latency=2

t_CK2,DQ

DOUT A₀

DOUT B₀

DOUT A₀

DOUT B₁

DOUT B₀

DOUT B₂DOUT B₃

CAS# latency=3

DOUT B₁

DOUT B₂DOUT B₃

t_CK3,DQ

The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a

Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write command to

suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with

high-impedance on the DQ pins must occur between the last read data and the Write command (refer

to the following three figures). If the data output of the burst read occurs at the second clock of the burst

write, the DQMs must be asserted (HIGH) at least one clock prior to the Write command to avoid

internal bus contention.

Confidential

-8/54-

Rev.1.0 Sep. 2015

1...5 6 789 10 11...54

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