Datasheet > AS4C2M32SA

AS4C2M32SA

更新时间： 2022-02-26 11:39:35

品牌	Logo	应用领域
ALSC		动态存储器
页数	文件大小	规格书
54页	5692K
描述
64Mb SDRAM AS4C2M32SA - 86pin TSOP II PACKAGE

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数据手册

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AS4C2M32SA 数据手册

AS4C2M32SA-6TIN

AS4C2M32SA-6TCN

AS4C2M32SA-7TCN

Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 3

shows the truth table for the operation commands.

Table 3. Truth Table (Note (1), (2))

Command

BankActivate

State CKE_n-1CKE_nDQM⁽⁶⁾BA0,1 A10 A0-9 CS# RAS# CAS# WE#

Idle⁽³⁾

Row address

BankPrecharge

PrechargeAll

Any

Active⁽³⁾

Idle

Column

address

(A0 ~ A7)

Write

Write and AutoPrecharge

Read

Column

address

(A0 ~ A7)

Read and Autoprecharge

Mode Register Set

No-Operation

OP code

Any

Active⁽⁴⁾

Burst Stop

Device Deselect

AutoRefresh

Any

Idle

SelfRefresh Entry

SelfRefresh Exit

Idle

(SelfRefresh)

Clock Suspend Mode Entry

Power Down Mode Entry

Active

Any⁽⁵⁾

Active

Clock Suspend Mode Exit

Power Down Mode Exit

Any

(PowerDown)

Data Write/Output Enable

Data Mask/Output Disable

Active

Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high

2. CKE_nsignal is input level when commands are provided.

CKE_n-1signal is input level one clock cycle before the commands are provided.

3. These are states of bank designated by BA signal.

4. Device state is 1, 2, 4, 8, and full page burst operation.

5. Power Down Mode can not enter in the burst operation.

When this command is asserted in the burst cycle, device state is clock suspend mode.

6. DQM0-3

Confidential

-6/54-

Rev.1.0 Sep. 2015

1...3 4 567 8 9...54

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