Datasheet > AS4C256M16D3

AS4C256M16D3

更新时间： 2022-02-26 12:04:06

品牌	Logo	应用领域
ALSC		/
页数	文件大小	规格书
83页	2083K
描述
Bidirectional differential data strobe

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AS4C256M16D3 数据手册

AS4C256M16D3

Figure 3. State Diagram

This simplified State Diagram is intended to provide an overview of the possible state transitions and the

commands to control them. In particular, situations involving more than one bank, the enabling or disabling

of on-die termination, and some other events are not captured in full detail

Power

applied

MRS,MPR,

Write

Leveling

Power

Reset

Procedure

Self

Refresh

Initialization

ZQCL

from any

state

MRS

Idle

RESET

ZQCL,ZQCS

Calibration

REF

Refreshing

ACT

ACT = Active

PRE = Precharge

Active

Power

Down

Precharge

Power

Down

Activating

PREA = Precharge All

MRS = Mode Register Set

REF = Refresh

RESET = Start RESET Procedure

Bank

Activating

Read = RD, RDS4, RDS8

Read A = RDA, RDAS4, RDAS8

Write = WR, WRS4, WRS8

READ

WRITE

Write A = WRA, WRAS4, WRAS8

ZQCL = ZQ Calibration Long

ZQCS = ZQ Calibration Short

READ

Reading

Writing

WRITE A

Writing

WRITE

PDE = Enter Power-down

PDX = Exit Power-down

SRE = Self-Refresh entry

SRX = Self-Refresh exit

REA

D A

MPR = Multi-Purpose Register

Reading

Automatic Sequence

Command Sequence

Precharging

Confidential

Rev. 3.0

Aug. /2014

1 2 3 456 7 8...83

下载PDF

与AS4C256M16D3相关器件

型号	品牌	描述	获取价格	数据表
AS4C256M16D3-12BCN	ALSC	Bidirectional differential data strobe	获取价格
AS4C256M16D3-12BIN	ALSC	Bidirectional differential data strobe	获取价格
AS4C256M16D3B	ALSC	12BCN 96 ball FBGA PACKAGE	获取价格
AS4C256M16D3B-12BCN	ALSC	Eight internal banks for concurrent operation	获取价格
AS4C256M16D3L-12BCN	ALSC	Supports JEDEC clock jitter specification	获取价格
AS4C256M16D3L-12BIN	ALSC	Supports JEDEC clock jitter specification	获取价格