Datasheet > AS4C256M16D3

AS4C256M16D3

更新时间： 2022-02-26 12:04:06

品牌	Logo	应用领域
ALSC		/
页数	文件大小	规格书
83页	2083K
描述
Bidirectional differential data strobe

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AS4C256M16D3 数据手册

AS4C256M16D3

4Gb (256M x 16 bit) DDR3 Synchronous DRAM (SDRAM)

Confidential

Features

(Rev. 3.0 Aug. /2014)

Overview

JEDEC Standard Compliant

The 4Gb Double-Data-Rate-3 DRAMs is double data

rate architecture to achieve high-speed operation. It is

internally configured as an eight bank DRAM.

The 4Gb chip is organized as 32Mbit x 16 I/Os x 8

bank devices. These synchronous devices achieve high

speed double-data-rate transfer rates of up to 1600

Mb/sec/pin for general applications.

The chip is designed to comply with all key DDR3

DRAM key features and all of the control and address

inputs are synchronized with a pair of externally

supplied differential clocks. Inputs are latched at the

cross point of differential clocks (CK rising and CK#

falling). All I/Os are synchronized with differential DQS

pair in a source synchronous fashion.



Power supplies: V_DD& V_DDQ= +1.5V  0.075V

Operating temperature:

- Commercial (0 ~ 95°C)

- Industrial (-40 ~ 95°C)

Supports JEDEC clock jitter specification

Fully synchronous operation

Fast clock rate: 800MHz

Differential Clock, CK & CK#

Bidirectional differential data strobe

-DQS & DQS#

8 internal banks for concurrent operation

8n-bit prefetch architecture

Internal pipeline architecture

Precharge & active power down

Programmable Mode & Extended Mode registers

Additive Latency (AL): 0, CL-1, CL-2

Programmable Burst lengths: 4, 8

Burst type: Sequential / Interleave



These devices operate with a single 1.5V ± 0.075V

power supply and are available in BGA packages.

 Output Driver Impedance Control

 8192 refresh cycles / 64ms

- Average refresh period

7.8μs @ -40℃≦TC≦ +85℃

3.9μs @ +85℃＜TC≦ +95℃

 Write Leveling

 OCD Calibration

 Dynamic ODT (Rtt_Nom & Rtt_WR)

RoHS compliant



Auto Refresh and Self Refresh

96-ball 9 x 13 x 1.2mm FBGA package

- All parts are ROHS Compliant

Table 1. Speed Grade Information

Speed Grade

Clock Frequency CAS Latency

t_RCD

t_RP

(ns)

DDR3-1600

800 MHz 11

13.75

Table 2 – Ordering Information for ROHS Compliant Products

Product part No

Org

Temperature

Package

AS4C256M16D3-12BCN

256M x 16

Commercial (Extended) 96-ball FBGA

0°C to 95°C

AS4C256M16D3-12BIN

256M x 16

Industrial

96-ball FBGA

-40°C to 95°C

Confidential

Rev. 3.0

Aug. /2014

123 4 5 6 7...83

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与AS4C256M16D3相关器件

型号	品牌	描述	获取价格	数据表
AS4C256M16D3-12BCN	ALSC	Bidirectional differential data strobe	获取价格
AS4C256M16D3-12BIN	ALSC	Bidirectional differential data strobe	获取价格
AS4C256M16D3B	ALSC	12BCN 96 ball FBGA PACKAGE	获取价格
AS4C256M16D3B-12BCN	ALSC	Eight internal banks for concurrent operation	获取价格
AS4C256M16D3L-12BCN	ALSC	Supports JEDEC clock jitter specification	获取价格
AS4C256M16D3L-12BIN	ALSC	Supports JEDEC clock jitter specification	获取价格