AS4C256K16FO
®
Refresh cycle
(V = 5V 10%, GND = 0V, T = 0° C to +70° C)
CC a
–25
–30
–35
–50
Standard
Symbol
Parameter
Min
10
7
Max Min Max Min Max Min Max Unit
Notes
tCSR
tCHR
tRPC
CAS setup time (CAS-before-RAS)
CAS hold time (CAS-before-RAS)
RAS precharge to CAS hold time
–
–
–
10
7
–
–
–
10
8
–
–
–
10
10
0
–
–
–
ns
ns
ns
3
3
0
0
0
CAS precharge time
(CAS-before-RAS counter test)
tCPT
8
–
8
–
8
–
8
–
ns
Output enable
(V = 5V 10%, GND = 0V, T = 0° C to +70° C)
CC a
–25
–30
–35
–50
Standard
Symbol
Parameter
Min Max Min Max Min Max Min Max Unit
Notes
tROH RAS hold time referenced to OE
5
–
5
–
5
–
8
–
6
–
5
–
5
–
8
–
10
–
5
–
5
–
8
–
10
–
5
–
8
–
8
–
10
–
ns
ns
ns
ns
ns
tOEA
tOED
tOEZ
tOEH
OE access time
OE to data delay
Output buffer turnoff delay from OE
OE command hold time
8
8
8
8
–
–
–
Self refresh cycle
(V = 5V 10%, GND = 0V, T = 0° C to +70° C)
CC
a
–25
–30
–35
–50
Standard
Symbol
Parameter
Min
Max Min Max Min Max Min Max Unit
Notes
tRASS RAS pulse width (CBR self refresh)
100K
RAS precharge time (CBR self refresh) 85
–
–
–
100K
85
–
–
–
100K
85
–
–
–
100K
85
–
–
–
ns
ns
ns
tRPS
tCHS CAS hold time (CBR self refresh)
30
30
30
30
Notes
1
2
3
I
, I , I , and I
depend on cycle rate.
CC6
CC1 CC3 CC4
I
and I
depend on output loading. Specified values are obtained with the output open.
CC4
CC1
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended
periods of bias without clocks (greater than 8 ms).
4
AC characteristics assume t = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V (min) ≥ GND and V (max) ≤
T IL IH
V
V
.
CC
5
6
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .
IL IH IL
IH
Operation within the t
(max) limit insures that t
(max) can be met. t
(max) is specified as a reference point only. If t
is greater than the speci-
RCD
RAC
RCD
RCD
fied t
(max) limit, then access time is controlled exclusively by t
.
RCD
CAC
7
Operation within the t
(max) limit insures that t
(max) can be met. t
RAC
(max) is specified as a reference point only. If t
is greater than the speci-
RAD
RAD
RAD
fied t
(max) limit, then access time is controlled exclusively by t .
AA
RAD
8
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either t or t must be satisfied for a read cycle.
9
RCH
RRH
10
11
t
t
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
OFF
, t
, t
, t
and t
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t
≥
WS
WCS WCH RWD CWD
AWD
(min) and t
≥ t
(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t
WS
WH
W
H
R
W
D
≥ t
(min), t
≥ t
(min) and t
≥ t
(min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If
AWD
RWD
CWD
CWD
AWD
neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t or t or t
.
CAP
CAA
CAC
14
t
≥ t to achieve t (min) and t
(max) values.
CAP
ASC
CP
PC
15 These parameters are sampled, but not 100% tested.
4/11/01; V.0.9.1
Alliance Semiconductor
P. 6 of 25
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