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AS4C16M16S-7TCN PDF预览

AS4C16M16S-7TCN

更新时间： 2024-02-06 19:35:40
品牌 Logo 应用领域
ALSC 时钟动态存储器ISM频段光电二极管内存集成电路
页数 文件大小 规格书
54页 2323K
描述
Programmable Mode registers

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AS4C16M16S-7TCN 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：TSOP2包装说明：0.400 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, TSOPII-54
针数：54Reach Compliance Code：compliant
风险等级：5.66访问模式：FOUR BANK PAGE BURST
最长访问时间：5.4 ns其他特性：AUTO/SELF REFRESH
JESD-30 代码：R-PDSO-G54长度：22.22 mm
内存密度：268435456 bit内存集成电路类型：SYNCHRONOUS DRAM
内存宽度：16功能数量：1
端口数量：1端子数量：54
字数：16777216 words字数代码：16000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：16MX16
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10.16 mmBase Number Matches：1

AS4C16M16S-7TCN 数据手册

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AS4C16M16S  
Table 3. Pin Details  
Symbol  
Type  
Description  
CLK  
Input  
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the  
positive edge of CLK. CLK also increments the internal burst counter and controls the  
output registers.  
CKE  
Input  
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE  
goes low synchronously with clock (set-up and hold time same as other inputs), the  
internal clock is suspended from the next clock cycle and the state of output and burst  
address is frozen as long as the CKE remains low. When all banks are in the idle state,  
deactivating the clock controls the entry to the Power Down and Self Refresh modes.  
CKE is synchronous except after the device enters Power Down and Self Refresh  
modes, where CKE becomes asynchronous until exiting the same mode. The input  
buffers, including CLK, are disabled during Power Down and Self Refresh modes,  
providing low standby power.  
BA0,BA1  
Input  
Bank Activate: BA0, BA1 input select the bank for operation.  
BA1  
0
BA0  
0
Select Bank  
BANK #A  
BANK #B  
BANK #C  
BANK #D  
0
1
1
0
1
1
A0-A12  
Input  
Address Inputs: A0-A12 are sampled during the BankActivate command (row address  
A0-A12) and Read/Write command (column address A0-A8 with A10 defining Auto  
Precharge) to select one location out of the 4M available in the respective bank. During  
a Precharge command, A10 is sampled to determine if all banks are to be precharged  
(A10 = HIGH). The address inputs also provide the op-code during a Mode Register Set  
command.  
CS#  
Input  
Input  
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command  
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for  
external bank selection on systems with multiple banks. It is considered part of the  
command code.  
RAS#  
Row Address Strobe: The RAS# signal defines the operation commands in  
conjunction with the CAS# and WE# signals and is latched at the positive edges of  
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either  
the BankActivate command or the Precharge command is selected by the WE# signal.  
When the WE# is asserted "HIGH," the BankActivate command is selected and the  
bank designated by BA is turned on to the active state. When the WE# is asserted  
"LOW," the Precharge command is selected and the bank designated by BA is switched  
to the idle state after the precharge operation.  
CAS#  
WE#  
Input  
Column Address Strobe: The CAS# signal defines the operation commands in  
conjunction with the RAS# and WE# signals and is latched at the positive edges of  
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is  
started by asserting CAS# "LOW." Then, the Read or Write command is selected by  
asserting WE# "LOW" or "HIGH."  
Input  
Input  
Write Enable: The WE# signal defines the operation commands in conjunction with the  
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is  
used to select the BankActivate or Precharge command and Read or Write command.  
LDQM,  
UDQM  
Data Input/Output Mask: Controls output buffers in read mode and masks  
Input data in write mode.  
DQ0-DQ15  
Input /  
Output  
Data I/O: The DQ0-15 input and output data are synchronized with the positive edges  
of CLK. The I/Os are maskabled during Reads and Writes.  
Confidential  
4
Rev. 3  
Feb. /2014  
1234567...54

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