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AS29F400T-90SC PDF预览

AS29F400T-90SC

更新时间： 2024-02-07 07:39:07
品牌 Logo 应用领域
ALSC 光电二极管内存集成电路
页数 文件大小 规格书
20页 444K
描述
Flash, 512KX8, 90ns, PDSO44, 0.600 INCH, SO-44

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AS29F400T-90SC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：0.600 INCH, SO-44
针数：44Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.51
风险等级：5.92最长访问时间：90 ns
其他特性：10K WRITE/ERASE CYCLE ENDURANCE; ALSO CONFIGURABLE AS 256K X 16备用内存宽度：8
启动块：TOP命令用户界面：YES
数据轮询：YES耐久性：10000 Write/Erase Cycles
JESD-30 代码：R-PDSO-G44JESD-609代码：e0
长度：28.2 mm内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1部门数/规模：1,2,1,7
端子数量：44字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP44,.63封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
编程电压：5 V认证状态：Not Qualified
就绪/忙碌：YES座面最大高度：2.8 mm
部门规模：16K,8K,32K,64K最大待机电流：0.000005 A
子类别：Flash Memories最大压摆率：0.05 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED切换位：YES
类型：NOR TYPE宽度：13.3 mm
Base Number Matches：1

AS29F400T-90SC 数据手册

 浏览型号AS29F400T-90SC的Datasheet PDF文件第3页浏览型号AS29F400T-90SC的Datasheet PDF文件第4页浏览型号AS29F400T-90SC的Datasheet PDF文件第5页浏览型号AS29F400T-90SC的Datasheet PDF文件第7页浏览型号AS29F400T-90SC的Datasheet PDF文件第8页浏览型号AS29F400T-90SC的Datasheet PDF文件第9页 
AS29F400  
Preliminary information  
®
Command definitions  
Item  
Description  
Initiate read or reset operations by writing the Read/Reset command sequence into the command  
register. This allows the microprocessor to retrieve data from the memory. Device remains in read  
mode until command register contents are altered.  
Reset/Read  
Device automatically powers up in read/reset state. This feature allows only reads, therefore  
ensuring no spurious memory content alterations during power up.  
AS29F400 provides manufacturer and device codes in two ways. External PROM programmers  
typically access the device codes by driving +12V on A9. AS29F400 also contains an ID Read  
command to read the device code with only +5V, since multiplexing +12V on address lines is  
generally undesirable.  
Initiate device ID read by writing the ID Read command sequence into the command register.  
Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command  
sequence with a read sequence from address XXX01h to return device code.  
ID Read  
To verify write protect status on sectors, read address XXX02h. Sector addresses A17–A12 produce  
a 1 on DQ0 for protected sector and a 0 for unprotected sector.  
Exit from ID read mode with Read/Reset command sequence.  
Holding RESET low for 500 ns resets the device, terminating any operation in progress; data  
handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driven  
low. RY/BY remains low until the RESET operation is completed. After RESET is set high, there is a  
delay of 1.5 µs for the device to permit read operations.  
Hardware Reset  
Programming the AS29F400 is a four bus cycle operation performed on a byte-by-byte or word-  
by-word basis. Two unlock write cycles precede the Program Setup command and program data  
write cycle. Upon execution of the program command, no additional CPU controls or timings are  
necessary. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched  
on the rising edge of CE or WE, whichever is first. The AS29F400’s automated on-chip program  
algorithm provides adequate internally-generated programming pulses and verifies the  
programmed cell margin.  
Check programming status by sampling data on the DATA polling (DQ7), toggle bit (DQ6), or  
RY/BY pin. The AS29F400 returns the equivalent data that was written to it (as opposed to  
complemented data), to complete the programming operation.  
Byte/word  
Programming  
The AS29F400 ignores commands written during programming. A hardware reset occurring  
during programming may corrupt the data at the programmed location.  
AS29F400 allows programming in any sequence, across any sector boundary. Changing data from  
0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1  
(exceeded programming time limits) or success according to DATA polling; reading this data after  
a read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high,  
and DQ6 continues to toggle. In this state, a Reset command returns the device to read mode.  
Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional  
unlock write cycles; and finally the Chip Erase command.  
Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip  
erase algorithm is invoked with the Chip Erase command sequence, AS29F400 automatically  
programs and verifies the entire memory array for an all-zero pattern prior to erase. The AS29F200  
returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding  
time limit.  
Chip Erase  
6
1...3456789...20

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