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AS29F400B-150TI PDF预览

AS29F400B-150TI

更新时间: 2024-01-31 04:38:18
品牌 Logo 应用领域
ALSC 光电二极管内存集成电路
页数 文件大小 规格书
20页 444K
描述
Flash, 512KX8, 150ns, PDSO48, 12 X 20 MM, TSOP1-48

AS29F400B-150TI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP1包装说明:12 X 20 MM, TSOP1-48
针数:48Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.92最长访问时间:150 ns
其他特性:10K WRITE/ERASE CYCLE ENDURANCE; ALSO CONFIGURABLE AS 256K X 16备用内存宽度:8
启动块:BOTTOM命令用户界面:YES
数据轮询:YES耐久性:10000 Write/Erase Cycles
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:18.4 mm内存密度:4194304 bit
内存集成电路类型:FLASH内存宽度:8
功能数量:1部门数/规模:1,2,1,7
端子数量:48字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP1
封装等效代码:TSSOP48,.8,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
编程电压:5 V认证状态:Not Qualified
就绪/忙碌:YES座面最大高度:1.2 mm
部门规模:16K,8K,32K,64K最大待机电流:0.000005 A
子类别:Flash Memories最大压摆率:0.05 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED切换位:YES
类型:NOR TYPE宽度:12 mm
Base Number Matches:1

AS29F400B-150TI 数据手册

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AS29F400  
Preliminary information  
®
Functional description  
The AS29F400 is a 4 megabit, 5 volt only Flash memory organized as 512K bytes of 8 bits each or 256K words of 16 bits each. For flexible  
erase and program capability, the 4 megabits of data is divided into 11 sectors: one 16K byte, two 8K byte, one 32K byte, and seven 64K  
byte. The ×8 data appears on DQ0–DQ7; the ×16 data appears on DQ0–DQ15. The AS29F400 is offered in JEDEC standard 44-pin SO and  
48-pin TSOP packages. This device is designed to be programmed and erased in-system with a single 5.0V V supply. The device can also  
CC  
be reprogrammed in standard EPROM programmers.  
The AS29F400 offers access times of 55/70/90/120/150 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate  
bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. Word mode (×16 output) is  
selected by BYTE = High and Byte mode (×8 output) is selected by BYTE = Low.  
The AS29F400 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command register using  
standard microprocessor write timings. An internal state-machine uses register contents to control the erase and programming circuitry.  
Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data from the device in the  
same manner as other Flash or EPROM devices. Use the program command sequence to invoke the automated on-chip programming  
algorithm that automatically times the program pulse widths and verifies proper cell margin. Use the erase command sequence to invoke the  
automated on-chip erase algorithm that preprograms the sector if it is not already programmed before executing the erase operation, times  
the erase pulse widths, and verifies proper cell margin.  
Boot sector architecture enables the device to boot from either the top (AS29F400T) or bottom (AS29F400B) sector. Sector erase  
architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically  
erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase operations in all or any combination of  
the eleven sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data  
from or program data to a sector that is not being erased. The chip erase command will automatically erase all unprotected sectors.  
A factory shipped AS29F400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one  
byte/word at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all  
bytes/words in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors.  
The device features single 5.0V power supply operation for read, write, and erase functions. Internally generated and regulated voltages are  
provided for the program and erase operations. A low V detector automatically inhibits write operations during power transtitions. The  
CC  
RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase operations. The device automatically  
resets to the read mode after program/erase operations are completed. DQ2 indicates which sectors are being erased.  
The AS29F400 resists accidental erasure or spurious programming signals resulting from power transitions. Control register architecture  
permits alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set  
to read mode with all program/erase commands disabled when V is less than V  
(lockout voltage). The command registers are not  
CC  
LKO  
affected by noise pulses of less than 5 ns on OE, CE, or WE. CE and WE must be logical zero and OE a logical one to initiate write commands.  
When the device’s hardware RESET pin is driven low, any program/erase operation in progress will be terminated and the internal state  
machine will be reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an automated on-  
chip program/erase algorithm, data in address locations being operated on will become corrupted and require rewriting. Resetting the  
device enables the system’s microprocessor to read boot-up firmware from the Flash memory.  
The AS29F400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes/words are programmed  
one at a time using EPROM programming mechanism of hot electron injection.  
2

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