Datasheet > AS29F010CW-15/XT

AS29F010CW-15/XT

更新时间： 2024-01-03 19:07:12

品牌	Logo	应用领域
AUSTIN		/
页数	文件大小	规格书
22页	242K
描述
128K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY

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技术参数
数据手册

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AS29F010CW-15/XT 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	0.600 INCH, CERAMIC, DIP-32	针数：	32
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.32.00.51	风险等级：	5.71
最长访问时间：	150 ns	JESD-30 代码：	R-CDIP-T32
JESD-609代码：	e0	长度：	42.418 mm
内存密度：	1048576 bit	内存集成电路类型：	FLASH
内存宽度：	8	功能数量：	1
端子数量：	32	字数：	131072 words
字数代码：	128000	工作模式：	ASYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	128KX8	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	编程电压：	5 V
认证状态：	Not Qualified	座面最大高度：	5.1308 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	MILITARY
端子面层：	TIN LEAD	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	类型：	NOR TYPE
宽度：	15.24 mm

AS29F010CW-15/XT 数据手册

FLASH

AS29F010

Austin Semiconductor, Inc.

erase circuits are disabled, and the device resets. Subsequent

writes are ignored until V_CCis greater than V_LKO. The system

must provide the proper signals to the control pins to prevent device power-up. No commands are required to retrieve data.

Reading Array Data

The device is automatically set to reading array data after

The device is also ready to read array data after completing an

Embedded Program or Embedded Erase algorithm.

unintentional writes when V_CCis greater than V_LKO

The system must issue the reset command to re-enable the

device for reading array data if DQ5 goes high, or while in the

autoselect mode. See the “Reset Command” section, next.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information. The

Read Operations table provides the read parameters, and the

Read Operation Timings diagram shows the timing diagram.

Write Pulse “Glitch” Protection

Noise pulses of less than 5ns (typical) on OE\, CE\, or WE\

do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE\ = V_IL,

CE\ = V_IHor WE\ = V_IH. To initiate a write cycle, CE\ and WE\

must be a logical zero while OE\ is a logical one.

Reset Command

Writing the reset command to the device resets the device

to reading array data. Address bits are don’t care for this

command.

The reset command may be written between the sequence

cycles in an erase command sequence before erasing begins.

This resets the device to reading array data. Once erasure

begins, however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the sequence

cycles in a program command sequence before programming

begins. This resets the device to reading array data. Once

programming begins, however, the device ignores reset com-

mands until the operation is complete.

The reset command may be written between the sequence

cycles in an autoselect command sequence. Once in the

autoselect mode, the reset command must be written to return

to reading array data.

Power-Up Write Inhibit

If WE\ = CE\ = V_ILand OE\ = V_IHduring power up, the

device does not accept commands on the rising edge of WE\.

The internal state machine is automatically reset to reading

array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or sequences

into the command register initiates device operations. The

Command Definitions table defines the valid register command

sequences. Writing incorrect address and data values or

writing them in the improper sequence resets the device to

reading array data.

All addresses are latched on the falling edge of WE\ or

CE\, whichever happens first. Refer to the appropriate timing

diagrams in the “AC Characteristics” section.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to reading array

data.

TABLE 3: Autoselect Codes (High Voltage Method)

A16 to A13 to

A14 A10

DESCRIPTION

CE\

OE\ WE\

A0 DQ7 to DQ0

Manufacturer ID

Device ID

01h

20h

01h

(protected)

Sector Protection

Verification

00h

(unprotected)

NOTE: L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t Care

AS29F010

Rev. 0.3 10/02

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

1...3 4 567 8 9...22

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