Datasheet > AS29F010CW-12/Q

AS29F010CW-12/Q

更新时间： 2024-01-27 06:13:53

品牌	Logo	应用领域
AUSTIN		/
页数	文件大小	规格书
22页	242K
描述
128K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY

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技术参数
数据手册

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AS29F010CW-12/Q 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	0.600 INCH, CERAMIC, DIP-32	针数：	32
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.32.00.51	风险等级：	5.66
最长访问时间：	120 ns	JESD-30 代码：	R-CDIP-T32
JESD-609代码：	e0	长度：	42.418 mm
内存密度：	1048576 bit	内存集成电路类型：	FLASH
内存宽度：	8	功能数量：	1
端子数量：	32	字数：	131072 words
字数代码：	128000	工作模式：	ASYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	128KX8	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	编程电压：	5 V
认证状态：	Not Qualified	座面最大高度：	5.1308 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	MILITARY
端子面层：	TIN LEAD	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	类型：	NOR TYPE
宽度：	15.24 mm	Base Number Matches：	1

AS29F010CW-12/Q 数据手册

FLASH

AS29F010

Austin Semiconductor, Inc.

DEVICE BUS OPERATIONS

Writing Commands/Command Sequences

To write a command or command sequence (which includes

programming data to the device and erasing sectors of memory),

This section describes the requirements and use of the

device bus operations, which are initiated through the internal

command register. The command register itself does not

occupy any addressable memory location. The register is

composed of latches that store the commands, along with the

address and data information needed to execute the command.

The contents of the register serve as inputs to the internal state

machine. The state machine outputs dictate the function of the

device. The appropriate device bus operations table lists the

inputs and control levels required, and the resulting output.

The following subsections describe each of these operations

in further detail.

the system must drive WE\ and CE\ to V_IL, and OE\ to V_IH.

An erase operation can erase one sector, multiple sectors,

or the entire device. The Sector Address Tables indicate the

address space that each sector occupies. A “sector address”

consists of the address bits required to uniquely select a

sector. See the “Command Definitions” section for details on

erasing a sector or the entire chip.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can then

read autoselect codes from the internal register (which is

separate from the memory array) on DQ7 - DQ0. Standard read

cycle timings apply in this mode. Refer to the “Autoselect

Mode” and “Autoselect Command Sequence” sections for more

information.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the CE\ and OE\ pins to V_IL. CE\ is the power control and

selects the device. OE\ is the output control and gates array

_CC2in the DC Characteristics table represents the active

current specification for the write mode. The “AC

Characteristics” section contains timing specification tables

and timing diagrams for write operations.

data to the output pins. WE\ should remain at V_IH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This ensures

that no spurious alteration of the memory content occurs

during the power transition. No command is necessary in this

mode to obtain array data. Standard microprocessor read cycles

that assert valid addresses on the device address inputs

produce valid data on the device data outputs. The device

remains enabled for read access until the command register

contents are altered.

See “Reading Array Data” for more information. Refer to

the AC Read Operations table for timing specifications and to

the Read Operations Timings diagram for the timing waveforms.

ICC1 in the DC Characteristics table represents the active

current specification for reading array data.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits on

DQ7 - DQ0. Standard read cycle timings and I_CCread

specifications apply. Refer to “Write Operation Status” for

more information, and to each AC Characteristics section in the

appropriate data sheet for timing diagrams.

TABLE 1: DEVICE BUS OPERATIONS

OPERATION

CE\

OE\

WE\

Addresses¹DQ0 - DQ7

Read

OUT

Write

Standby

± 0.5V

High-Z

Output Disable

Hardware Reset

High-Z

NOTES:

1. Addresses are A16:A0.

2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/

Unprotection” section.

AS29F010

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

Rev. 0.3 10/02

1 2 345 6 7...22

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