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AS1334-BTDT-30 PDF预览

AS1334-BTDT-30

更新时间: 2024-01-12 02:00:18
品牌 Logo 应用领域
艾迈斯 - AMSCO 转换器
页数 文件大小 规格书
17页 1733K
描述
650mA, Ultra low Ripple Step Down DC/DC Converter

AS1334-BTDT-30 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.74Base Number Matches:1

AS1334-BTDT-30 数据手册

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AS1334  
Datasheet - Detailed Description  
Figure 23. Typical Operating System Circuit  
3.3 µH  
PVIN  
SW  
FB  
VIN  
VOUT  
2.7V to 5.5V  
10 µF  
VDD  
EN  
AS1334  
10 µF  
System  
Controller  
POK  
ON/OFF  
SGND  
PGND  
Operating the AS1334  
AS1334’s control block turns on the internal PFET (P-channel MOSFET) switch during the first part of each switching  
cycle, thus allowing current to flow from the input through the inductor to the output filter capacitor and load. The  
inductor limits the current to a ramp with a slope of around (VIN - VOUT) / L, by storing energy in a magnetic field.  
During the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and  
then turns the NFET (N-channel MOSFET) synchronous rectifier on. As a result, the inductor’s magnetic field  
collapses, generating a voltage that forces current from ground through the synchronous rectifier to the output filter  
capacitor and load.  
While the stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope  
around VOUT / L. The output filter capacitor stores charge when the inductor current is high, and releases it when low,  
smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to  
control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave  
formed by the switch and synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter  
capacitor.  
The output voltage is equal to the average voltage at the SW pin.  
While in operation, the output voltage is regulated by switching at a constant frequency and then modulating the  
energy per cycle to control power to the load. Energy per cycle is set by modulating the PFET switch on-time pulse  
width to control the peak inductor current. This is done by comparing the signal from the current-sense amplifier with a  
slope compensated error signal from the voltage-feedback error amplifier. At the beginning of each cycle, the clock  
turns on the PFET switch, causing the inductor current to ramp up. When the current sense signal ramps past the error  
amplifier signal, the PWM comparator turns off the PFET switch and turns on the NFET synchronous rectifier, ending  
the first part of the cycle.  
If an increase in load pulls the output down, the error amplifier output increases, which allows the inductor current to  
ramp higher before the comparator turns off the PFET. This increases the average current sent to the output and  
adjusts for the increase in the load. Before appearing at the PWM comparator, a slope compensation ramp from the  
oscillator is subtracted from the error signal for stability of the current feedback loop. The minimum on time of PFET in  
PWM mode is 50ns (typ.)  
www.austriamicrosystems.com  
Revision 1.04  
11 - 17  

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