Datasheet > AS1310-BTDT-25

AS1310-BTDT-25

更新时间： 2024-02-17 05:22:27

品牌	Logo	应用领域
艾迈斯 - AMSCO		转换器升压转换器
页数	文件大小	规格书
20页	1271K
描述
Ultra Low Quiescent Current, Hysteretic DC-DC Step-Up Converter

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AS1310-BTDT-25 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	7.89	Base Number Matches：	1

AS1310-BTDT-25 数据手册

AS1310

Datasheet - Application Information

Table 4. Recommended Inductors

Part Number

DCR

Current Rating

0.54A

Dimensions (L/W/T)

3.2x2.5x1.55 mm

3.0x3.0x1.1 mm

4.0x4.0x1.1 mm

Manufacturer

LQH32CN6R8M53L

LQH3NPN6R8NJ0L

LQH44PN6R8MJ0L

6.8µH

250mΩ

210mΩ

143mΩ

Murata

www.murata.com

0.7A

0.72A

9.5 Capacitor Selection

The convertor requires three capacitors. Ceramic X5R or X7R types will minimize ESL and ESR while maintaining capacitance at rated voltage

over temperature. The VIN capacitor should be 22µF. The VOUT capacitor should be between 22µF and 47µF. A larger output capacitor should

be used if lower peak to peak output voltage ripple is desired. A larger output capacitor will also improve load regulation on VOUT. See Table 5

for a list of capacitors for input and output capacitor selection.

Table 5. Recommended Input and Output Capacitors

Part Number

TC Code

X5R

Rated Voltage

6.3V

Dimensions (L/W/T)

0805, T=1.25mm

1206, T=1.6mm

Manufacturer

GRM21BR60J226ME99

GRM31CR61C226KE15

GRM31CR60J475KA01

22µF

47µF

Murata

www.murata.com

X5R

16V

X5R

6.3V

1206, T=1.6mm

On the pin REF a 10nF capacitor with an Insulation resistance >1GΩ is recommended.

Table 6. Recommended Capacitors for REF

Insulation

Resistance

Rated

Voltage

Part Number

TC Code

Dimensions (L/W/T)

Manufacturer

GRM188R71C104KA01

GRM31CR61C226KE15

100nF

X7R

>5GΩ

16V

0603, T=0.8mm

0805, T=1.25mm

Murata

www.murata.com

50V

9.6 Layout Considerations

Relatively high peak currents of 480mA (max) circulate during normal operation of the AS1310. Long printed circuit tracks can generate

additional ripple and noise that mask correct operation and prove difficult to “de-bug” during production testing. Referring to Figure 1, the input

loop formed by C1, VIN and GND pins should be minimized. Similarly, the output loop formed by C2, VOUT and GND should also be minimized.

Ideally both loops should connect to GND in a “star” fashion. Finally, it is important to return CREF to the GND pin directly.

www.austriamicrosystems.com/DC-DC_Step-Up/AS1310

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