AP2161A/ AP2171A
Electrical Characteristics (@TA = +25°C, VIN = +5V, unless otherwise specified.)
Symbol
VUVLO
ISHDN
IQ
Parameter
Test Conditions
Min
1.6
—
Typ
1.9
0.5
45
Max
2.5
1
Unit
V
Input UVLO
RLOAD = 1kΩ
Input Shutdown Current
Input Quiescent Current
Input Leakage Current
Reverse Leakage Current
uA
µA
µA
µA
Disabled, IOUT = 0
Enabled, IOUT = 0
—
70
Disabled, OUT grounded
—
—
1
ILEAK
IREV
—
1
—
Disabled, VIN = 0V, VOUT = 5V, IREV at VIN
SOT25, MSOP-8EP, SO-8
U-DFN2018-6
—
95
115
110
140
140
170
—
TA = +25°C
VIN = 5V,
IOUT = 1A
—
90
—
—
-40°C ≤ TA ≤ +85°C
TA = +25°C
Switch On-Resistance
mΩ
RDS(ON)
—
120
—
VIN = 3.3V,
IOUT = 1A
—
-40°C ≤ TA ≤ +85°C
Short-Circuit Current Limit
Over-Load Current Limit
Current Limiting Trigger Threshold
EN Input Leakage
—
1.2
1.5
A
ISHORT
ILIMIT
ITrig
Enabled into short circuit, CL = 68µF
VIN = 5V, VOUT = 4.6V, CL = 68µF, -40°C ≤ TA ≤ +85°C
Output Current Slew rate (<100A/s) , CL=68µF
VEN = 5V
1.1
1.9
A
—
—
—
—
—
—
2.0
—
—
1
A
µA
ms
ms
ms
ms
ISINK
Output Turn-On Delay Time
Output Turn-On Rise Time
Output Turn-Off Delay Time
Output Turn-Off Fall Time
0.05
0.6
—
1.5
—
0.1
tD(ON)
tR
tD(OFF)
tF
CL = 1µF, RLOAD = 10Ω
CL = 1µF, RLOAD = 10Ω
0.01
0.05
CL = 1µF, RLOAD = 10Ω
CL = 1µF, RLOAD = 10Ω
Fault Flag
RFLG
tBlank
FLG Output FET On-Resistance
FLG Blanking Time
—
4
20
7
40
15
Ω
IFLG = 10mA
ms
CIN = 10µF, CL = 68µF
Over-Temperature Protection
Thermal Shutdown Threshold
—
—
—
—
140
25
°C
TSHDN
THYS
Enabled, RLOAD = 1kΩ
-
Thermal Shutdown Hysteresis
°C
SO-8 (Note 5)
—
—
—
—
110
60
—
—
—
—
°C/W
°C/W
°C/W
°C/W
MSOP-8EP (Note 6)
SOT25 (Note 7)
U-DFN2018-6 (Note 8)
Thermal Resistance Junction-to-
Ambient
θJA
157
70
Notes:
5. Test condition for SO-8: Device mounted on FR-4, 2oz copper, with minimum recommended pad layout.
6. Test condition for MSOP-8EP: Device mounted on 2” x 2” FR-4 substrate PC board, 2oz copper, with minimum recommended pad on top layer and
thermal vias to bottom layer ground plane.
7. Test condition for SOT25: Device mounted on FR-4, 2oz copper, with minimum recommended pad layout.
8. Test condition for U-DFN2018-6: Device mounted on FR-4 2-layer board, 2oz copper, with minimum recommended pad on top layer and 3 vias to bottom
layer 1.0”x1.4” ground plane.
4 of 18
www.diodes.com
March 2015
© Diodes Incorporated
AP2161A/AP2171A
Document number: DS37617 Rev. 1 - 2