PRELIMINARY
Am45DL3208G
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash
Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Pseudo Static RAM
DISTINCTIVE CHARACTERISTICS
■ 20 year data retention at 125°C
MCP Features
■ Power supply voltage of 2.7 to 3.3 volt
—
Reliable operation for the life of the system
SOFTWARE FEATURES
■ High performance
—
Access time as fast as 70 ns
■ Data Management Software (DMS)
■ Package
—
AMD-supplied software manages data programming,
enabling EEPROM emulation
Eases historical sector erase flash limitations
—
73-Ball FBGA
—
■ Operating Temperature
■ Supports Common Flash Memory Interface (CFI)
—
–40°C to +85°C
■ Program/Erase Suspend/Erase Resume
Flash Memory Features
—
Suspends program/erase operations to allow
programming/erasing in same bank
ARCHITECTURAL ADVANTAGES
■ Data# Polling and Toggle Bits
■ Simultaneous Read/Write operations
—
Provides a software method of detecting the status of
program or erase cycles
—
Data can be continuously read from one bank while
executing erase/program functions in another bank.
Zero latency between read and write operations
■ Unlock Bypass Program command
—
—
Reduces overall programming time when issuing multiple
program command sequences
■ Flexible Bank™ architecture
—
Read may occur in any of the three banks not being written
or erased.
HARDWARE FEATURES
—
Four banks may be grouped by customer to achieve desired
bank divisions.
■ Any combination of sectors can be erased
■ Ready/Busy# output (RY/BY#)
■ Manufactured on 0.17 µm process technology
—
Hardware method for detecting program or erase cycle
completion
■ SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector
—
Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
■ Hardware reset pin (RESET#)
—
Hardware method of resetting the internal state machine to
the read mode
■ WP#/ACC input pin
—
Customer lockable: Sector is one-time programmable. Once
sector is locked, data cannot be changed.
—
Write protect (WP#) function protects sectors 0 and 1
(bottom boot) or 69 and 70 (top boot), regardless of sector
protect status
■ Zero Power Operation
Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
—
Acceleration (ACC) function accelerates program timing
—
■ Sector protection
—
Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
Temporary Sector Unprotect allows changing data in
protected sectors in-system
■ Top or bottom boot sectors
■ Compatible with JEDEC standards
—
Pinout and software compatible with single-power-supply
flash standard
—
PERFORMANCE CHARACTERISTICS
Pseudo SRAM Features
■ Power dissipation
■ High performance
—
—
Access time as fast as 70 ns
Program time: 4 µs/word typical utilizing Accelerate function
—
—
Operating: 30 mA maximum
Standby: 100 µA maximum
■ Ultra low power consumption (typical values)
■ CE1s# and CE2s Chip Select
—
—
—
2 mA active read current at 1 MHz
10 mA active read current at 5 MHz
200 nA in standby or automatic sleep mode
■ Power down features using CE1s# and CE2s
■ Data retention supply voltage: 2.7 to 3.3 volt
■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
■ Minimum 1 million write cycles guaranteed per sector
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 26460 Rev: B Amendment/+1
Issue Date: March 12, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.