Am29DL640G
64 Megabit (8 M x 8-Bit/4 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
This product has been retired and is not recommended for designs. For new and current designs, S29JL064H (for TSOP packages) and S29PL064J (for FBGA packages) supersede
AM29DL640G as the factory-recommended migration path. Please refer to each respective datasheets for specifications and ordering information. Availability of this document is retained
for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■ Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
ARCHITECTURAL ADVANTAGES
■ Simultaneous Read/Write operations
— 10 mA active read current at 5 MHz
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— 200 nA in standby or automatic sleep mode
— Zero latency between read and write operations
■ Minimum 1 million erase cycles guaranteed per
sector
■ 20 year data retention at 125°C
— Reliable operation for the life of the system
■ Flexible BankTM architecture
— Read may occur in any of the three banks not being
written or erased.
— Four banks may be grouped by customer to achieve
desired bank divisions.
SOFTWARE FEATURES
■ Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
■ Boot Sectors
— Top and bottom boot sectors in the same device
— Any combination of sectors can be erased
— Eases historical sector erase flash limitations
■ Manufactured on 0.17 µm process technology
■ Supports Common Flash Memory Interface (CFI)
■ Erase Suspend/Erase Resume
■ SecSi™ (Secured Silicon) Sector: Extra 256 Byte
sector
— Suspends erase operations to allow reading from
other sectors in same bank
— Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
■ Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■ Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
— Customer lockable: One-time programmable only.
Once locked, data cannot be changed
■ Zero Power Operation
HARDWARE FEATURES
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
■ Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■ Compatible with JEDEC standards
■ Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
— Pinout and software compatible with
single-power-supply flash standard
PACKAGE OPTIONS
■ WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1,
140, and 141, regardless of sector protect status
■ 63-ball Fine Pitch BGA
■ 64-ball Fortified BGA
■ 48-pin TSOP
— Acceleration (ACC) function accelerates program
timing
■ Sector protection
PERFORMANCE CHARACTERISTICS
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
■ High performance
— Access time as fast as 70 ns
— Program time: 4 µs/word typical utilizing Accelerate
function
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
Publication# 25693 Rev: B Amendment 5
Issue Date: June 6, 2005
Refer to AMD’s Website (www.amd.com) for the latest information.
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