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AM29DL164DT120PCI PDF预览

AM29DL164DT120PCI

更新时间: 2024-01-02 11:57:58
品牌 Logo 应用领域
飞索 - SPANSION 内存集成电路闪存
页数 文件大小 规格书
57页 1243K
描述
Flash, 1MX16, 120ns, PBGA64, 13 X 11 MM, 1.0 MM PITCH, FBGA-64

AM29DL164DT120PCI 技术参数

是否Rohs认证: 不符合生命周期:Active
Reach Compliance Code:compliant风险等级:5.87
最长访问时间:120 ns备用内存宽度:8
启动块:TOP命令用户界面:YES
通用闪存接口:YES数据轮询:YES
JESD-30 代码:S-PBGA-B64内存密度:16777216 bit
内存集成电路类型:FLASH部门数/规模:8,31
端子数量:64字数:1048576 words
字数代码:1000000最高工作温度:85 °C
最低工作温度:-40 °C组织:1MX16
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA64,8X8,40封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
电源:3/3.3 V认证状态:Not Qualified
就绪/忙碌:YES部门规模:8K,64K
最大待机电流:0.000005 A子类别:Flash Memories
最大压摆率:0.045 mA表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM切换位:YES
类型:NOR TYPEBase Number Matches:1

AM29DL164DT120PCI 数据手册

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D A T A S H E E T  
GENERAL DESCRIPTION  
The Am29DL16xD family consists of 16 megabit, 3.0  
volt-only flash memory devices, organized as 1,048,576  
words of 16 bits each or 2,097,152 bytes of 8 bits each.  
Word mode data appears on DQ0–DQ15; byte mode  
data appears on DQ0–DQ7. The device is designed to  
be programmed in-system with the standard 3.0 volt  
VCC supply, and can also be programmed in standard  
EPROM programmers.  
or both. Customer Lockable parts may utilize the Se-  
cured Silicon Sector as bonus space, reading and  
writing like any other flash sector, or may permanently  
lock their own code there.  
DMS (Data Management Software) allows systems to  
easily take advantage of the advanced architecture of  
the simultaneous read/write product line by allowing re-  
moval of EEPROM devices. DMS will also allow the  
system software to be simplified, as it will perform all  
functions necessary to modify data in file structures, as  
opposed to single-byte modifications. To write or up-  
date a particular piece of data (a phone number or  
configuration data, for example), the user only needs to  
state which piece of data is to be updated, and where  
the updated data is located in the system. This is an  
advantage compared to systems where user-written  
software must keep track of the old data location, sta-  
tus, logical to physical translation of the data onto the  
Flash memory device (or memory devices), and more.  
Using DMS, user-written software does not need to in-  
terface with the Flash memory directly. Instead, the  
user's software accesses the Flash memory by calling  
one of only six functions. AMD provides this software to  
simplify system design and software integration efforts.  
The device is available with an access time of 70, 90,  
or 120 ns. The devices are offered in 48-pin TSOP,  
48-ball Fine-pitch BGA, 48-ball Very Thin Profile  
Fine-pitch BGA, and 64-ball Fortified BGA packages.  
Standard control pins—chip enable (CE#), write enable  
(WE#), and output enable (OE#)—control normal read  
and write operations, and avoid bus contention issues.  
The device requires only a single 3.0 volt power sup-  
ply for both read and write functions. Internally  
generated and regulated voltages are provided for the  
program and erase operations.  
Simultaneous Read/Write Operations with  
Zero Latency  
The Simultaneous Read/Write architecture provides si-  
multaneous operation by dividing the memory space  
into two banks. The device can improve overall system  
performance by allowing a host system to program or  
erase in one bank, then immediately and simulta-  
neously read from the other bank, with zero latency.  
This releases the system from waiting for the comple-  
tion of program or erase operations.  
The device offers complete compatibility with the  
JEDEC single-power-supply Flash command set  
standard. Commands are written to the command reg-  
ister using standard microprocessor write timings.  
Reading data out of the device is similar to reading  
from other Flash or EPROM devices.  
The host system can detect whether a program or  
erase operation is complete by using the device status  
bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2  
(toggle bits). After a program or erase cycle has been  
completed, the device automatically returns to reading  
array data.  
The Am29DL16xD devices uses multiple bank archi-  
tectures to provide flexibility for different applications.  
Four devices are available with these bank sizes:  
Device  
DL161  
DL162  
DL163  
DL164  
Bank 1  
0.5 Mb  
2 Mb  
Bank 2  
15.5 Mb  
14 Mb  
12 Mb  
8 Mb  
The sector erase architecture allows memory sectors  
to be erased and reprogrammed without affecting the  
data contents of other sectors. The device is fully  
erased when shipped from the factory.  
4 Mb  
8 Mb  
Am29DL16xD Features  
Hardware data protection measures include a low  
VCC detector that automatically inhibits write operations  
during power transitions. The hardware sector pro-  
tection feature disables both program and erase  
operations in any combination of the sectors of mem-  
ory. This can be achieved in-system or via  
programming equipment.  
The Secured Silicon Sector is an extra sector capa-  
ble of being permanently locked by AMD or customers.  
The Secured Silicon Sector Indicator Bit (DQ7) is  
permanently set to a 1 if the part is factory locked,  
and set to a 0 if customer lockable. This way, cus-  
tomer lockable parts can never be used to replace a  
factory locked part. Current version of device has 64  
Kbytes; future versions will have only 256 bytes.  
This should be considered during system design.  
The device offers two power-saving features. When  
addresses have been stable for a specified amount of  
time, the device enters the automatic sleep mode.  
The system can also place the device into the  
standby mode. Power consumption is greatly re-  
duced in both modes.  
Factory locked parts provide several options. The Se-  
cured Silicon Sector may store a secure, random 16  
byte ESN (Electronic Serial Number), customer code  
(programmed through AMD’s ExpressFlash service),  
4
Am29DL16xD  
21533E6 February 26, 2009  

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