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AM27C512-200DC PDF预览

AM27C512-200DC

更新时间: 2024-09-25 20:23:15
品牌 Logo 应用领域
飞索 - SPANSION 可编程只读存储器电动程控只读存储器内存集成电路
页数 文件大小 规格书
12页 175K
描述
UVPROM, 64KX8, 200ns, CMOS, CDIP28, CERAMIC, DIP-28

AM27C512-200DC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP28,.6针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.61风险等级:5.4
最长访问时间:200 nsI/O 类型:COMMON
JESD-30 代码:R-CDIP-T28JESD-609代码:e0
长度:37.147 mm内存密度:524288 bit
内存集成电路类型:UVPROM内存宽度:8
湿度敏感等级:1功能数量:1
端子数量:28字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX8输出特性:3-STATE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP28,.6封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:5.588 mm
最大待机电流:0.0001 A子类别:EPROMs
最大压摆率:0.025 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:15.24 mmBase Number Matches:1

AM27C512-200DC 数据手册

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FINAL  
Am27C512  
512 Kilobit (64 K x 8-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
n Fast access time  
n Latch-up protected to 100 mA from –1 V to  
VCC + 1 V  
— Speed options as fast as 55 ns  
n Low power consumption  
n High noise immunity  
n Versatile features for simple interfacing  
— Both CMOS and TTL input/output compatibility  
— Two line control functions  
— 20 µA typical CMOS standby current  
n JEDEC-approved pinout  
n Single +5 V power supply  
n Standard 28-pin DIP, PDIP, and 32-pin PLCC  
n ±10% power supply tolerance standard  
n 100% Flashrite™ programming  
— Typical programming time of 8 seconds  
packages  
GENERAL DESCRIPTION  
The Am27C512 is a 512-Kbit, ultraviolet erasable pro-  
grammable read-only memory. It is organized as 64K  
words by 8 bits per word, operates from a single +5 V  
supply, has a static standby mode, and features fast  
single address location programming. Products are  
available in windowed ceramic DIP packages, as well  
as plastic one time programmable (OTP) PDIP and  
PLCC packages.  
thus eliminating bus contention in a multiple bus micro-  
processor system.  
AMD’s CMOS process technology provides high  
speed, low power, and high noise immunity. Typical  
power consumption is only 80 mW in active mode, and  
100 µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random. The device supports AMD’s  
Flashrite programming algorithm (100 µs pulses), re-  
sulting in a typical programming time of 8 seconds.  
Data can be typically accessed in less than 55 ns, al-  
lowing high-performance microprocessors to operate  
without any WAIT states. The device offers separate  
Output Enable (OE#) and Chip Enable (CE#) controls,  
BLOCK DIAGRAM  
Data Outputs  
DQ0–DQ7  
V
V
CC  
SS  
Output Enable  
Chip Enable  
and  
OE#/V  
PP  
Output  
Buffers  
CE#  
Prog Logic  
Y
Y
Gating  
Decoder  
A0–A15  
Address  
Inputs  
524,288  
Bit Cell  
Matrix  
X
Decoder  
08140J-1  
Publication# 08140 Rev: J Amendment/+2  
Issue Date: June 1, 1999  

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