Datasheet > ALVCH16832DGG

ALVCH16832DGG

更新时间： 2022-12-01 21:22:22

品牌	Logo	应用领域
恩智浦 - NXP		驱动光电二极管输出元件
页数	文件大小	规格书
12页	89K
描述
IC ALVC/VCX/A SERIES, 7 1-BIT DRIVER, TRUE OUTPUT, PDSO64, 6.10 MM, PLASTIC, MO-153, SOT-646-1, TSSOP-64, Bus Driver/Transceiver

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ALVCH16832DGG 数据手册

Philips Semiconductors

Product data

7-bit to 28-bit address register/driver with

3-state outputs

74ALVCH16832

PARAMETER MEASUREMENT INFORMATION

= 1.8 V

2 × V

1 kΩ

Open

GND

TEST

From Output

Under Test

Open

2 × V

= 30 pF

1 kΩ

(see Note A)

PLZ PZL CC

GND

PHZ PZH

Load Circuit

Timing

Input

0 V

Input

0 V

Voltage Waveforms

Pulse Duration

Data

Input

0 V

Voltage Waveforms

Setup and Hold Times

Output

Control

(low-level

enabling)

0 V

PZL

PLZ

Input

Output

Waveform 1

0 V

+ 0.15 V

S1 at 2 x V

(see Note B)

PLH

PHL

PZH

PHZ

Output

Waveform 2

S1 at GND

– 0.15 V

0 V

(see Note B)

Voltage Waveforms

Propagation Delay Times

Voltage Waveforms

Enable and Disable Times

SV01911

NOTES:

A. C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. t

F. t

G. t

and t

are the same as t

dis

PLZ

PZL

PLH

PHZ

PZH

are the same as t

and t

are the same as t .

PHL

Figure 1. Load circuit and voltage waveforms

2001 Dec 14

1...4 5 678 9 10...12

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