AL8853AQ
Functional Description
The AL8853AQ is a LED driver controller designed for boost and SEPIC controllers in a constant-frequency mode. It implements a peak current-
mode control scheme and an internal transconductance amplifier to accurately control the output current over a wide input and load conditions.
The AL8853AQ has comprehensive protection features such as power MOSFET overcurrent protection (OCP), output overvoltage protection (OVP),
diode & inductor short protection, LED cathode short to GND protection, IC power-supply undervoltage lockout (UVLO), LED open protection, VOUT
short protection and overtemperature protection (OTP).
Startup
AL8853AQ is enabled by applying a voltage of greater than 2.5V to the PWM pin. The PWM pin is pulled down to GND with an on-chip 220kΩ
resistor. When the first rising edge is applied to the PWM pin, the AL8853AQ will power up immediately, and remains powered up until the PWM
input is lower than 1.3V for at least 20ms (typical). At this time the IC will enter standby mode. At standby mode, the current consumption of the
AL8853AQ will be lower than 130µA (typical). Once AL8853AQ is enabled, the internal 5V regulator will be activated and consumes less than 4mA.
When PWM is active-high, the AL8853AQ checks the topology connection first. The IC monitors the OVP pin to see if the boost Schottky diode is
connected or the output is short to GND. If the voltage at OVP pin is lower than 100mV, the output will be disabled. Due to the output voltage is zero
before system startup in SEPIC application, it’s necessary to supply a 0.2V offset on OVP pin for SEPIC topology, otherwise system may not start
up normally. The AL8853AQ will also check other faults (UVLO, CS high, CMP high, FB high, OCP and OTP), and the boost controller will boost up
the output with the internal soft-start if no fault conditions.
UVLO
AL8853AQ contains an undervoltage lockout (UVLO) protection. AL8853AQ is not turned on until the power supply VIN has reached 5.4V (typical).
Whenever the input voltage falls below approximately 5.0V (typical), the device is turned off. The UVLO circuit has a hysteresis of 400mV.
LED Current Regulation
The AL8853AQ senses the FB pin voltage to control the LED current. The error between the sensed voltage and the internal FB reference voltage
is amplified and compared to the CS pin sensing current signal plus the slope compensation to determine the power MOSFET on-time. The error
amplifier sources or sinks current to the COMP pin to adjust the required inductor current responding to the load changes. The slope compensation
signal is added to the current-sense signal to guarantee system stability at high duty cycle.
The error amplifier reference is set by internal reference voltage and the PWM duty cycle at PWM pin. And the average LED current is approximated
by Equation 1:
퐼퐿퐸퐷[mA] = 200푚푉∙퐷푈푇푌 ……………………………………………………… (1)
푅퐹퐵[Ω]
AL8853AQ enters the pulse-skip mode at light load to improve efficiency and prevent overcharging the output capacitor. AL8853AQ turns the GATE
signal high for a minimum on-time (typical 600ns), and remains low until another pulse is needed to maintain the boost-controller output voltage.
Dimming Control
The LED current is controlled by the external PWM signal with different duty cycles. The AL8853AQ can support PWM signals with frequency ranging
from 5kHz to 50kHz, and the PWM signal shall be higher than 2.5V for high logic and be lower than 1.3V for low logic. An internal square wave with
duty cycle same as the external PWM signal is filtered to provide reference voltage of EA input, which determines the FB reference.
Slope Compensation
The AL8853AQ adopts a peak current-mode control scheme. The main advantages of current mode are inherent cycle-by-cycle current limit of the
power MOSFET and simple control loop characteristics. However, current-mode control could cause the sub-harmonic oscillation for duty cycles
greater than 50%, leading to system instability. The AL8853AQ has a build-in slope compensation to avoid the sub-harmonic oscillation.
Input of PWM Comparator Waveform
Se
Sf
Sn
ΔI(n+2)
ΔI(n)
Vsense
ΔI(n+1)
time
Time
Figure 4. Sub-Harmonic Oscillation at Duty > 50% and Compensation Slope to Avoid Sub-Harmonic Oscillation
7 of 15
September 2023
AL8853AQ
© 2023 Copyright Diodes Incorporated. All Rights Reserved.
www.diodes.com
Document number: DS45623 Rev. 2 - 2
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