Datasheet > AL3000

AL3000

更新时间： 2024-09-28 06:36:55

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
2页	24K
描述
IP Frame Routing Processor

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AL3000 数据手册

AL3000

Advance Information

IP Frame Routing Processor

•

Provides routing functions to Allayer’s RoX-II

bus Ethernet Switching devices

Supports up to 32 Fast Ethernet or dual Gigabit • Programmable replacement of MAC and/or IP

ports on the RoX-II bus

High performance Network (Layer 3) and

Transport (Layer 4) address look-up engine

Layer 2-, 3-, or 4-flow packet classification

Programmable key search based on MAC and IP

source and destination address, TCP socket,

UDP socket or IP protocol number

Supports up to 131,072 individual host route

entries

Supports 802.1q priority schemes and provides

four Quality of Service (QoS) queues

Provides Network Address Translation (NAT)

per route database entry

Provides support for IP Proxy Services with re- • Six high-speed DMA engines

mappng of Layer 4 Socket replacements

•

Re-assigns VLAN tag and priority for each

routed frame

fields with associated Layer 3 and Layer 4

check-sum recalculation

Supports 802.3ad port aggregation

Supports virtually unlimited physical inter-

faces and as many logical interfaces as soft-

ware is capable

Congestion control for each physical interface

and the overall routing engine

Packet bandwidth control for each Layer 3 or

Layer 4 flow

Layer 3 buffer pool of up to 1024 frames

Provides Ethernet, Bridge, and RMON MIB

support for RoX II bus devices

•

0.25 micron, 2.5V / 3.3V CMOS technology

456-pin BGA package

Programmable entry aging via internal timers

and via external real-time clock

Interface to Switch Device

32-bit uP

Bus

Processor

Interface/

DMA Control

Management

DMA Host

Engine

I/O Packet

Engines

RoX II

Interface

RoX II

Ring Control

Command

Interpreter

3.3 Volts

GND

Memory &

Queue

Server

Parser / Result

Engine

CLK

Engine

Reset

Output

Queue/

RAM Control

Scan/Test

SGRAM Interface

Packet Memory

Search Memory

SGRAM 4-8 MB

SGRAM 2 MB

Figure 1

System Block Diagram

Reference Only / Allayer Confidential

中文翻译

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