Datasheet > AL1214H

AL1214H

更新时间： 2022-01-19 05:40:00

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AL1214H 数据手册

10BIT 80MSPS DAC

TIMING DIAGRAM

AL1214H

D[9:0]

CLK

Tset

0.1%

50%

1 clock pipeline delay

NOTES

1. Output delay measured from the 50%point of the rising edge of CLK to the full scale transition

2. Settling time measured from the 50% point of full scale transition to the output remaining within ±1 , ±2LSB.

3. Output rise/fall time measured between the 10% and 90% points of full scale transition.

SEC ASIC

ANALOG

6 / 12

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